Pipeline synthesis and optimization of FPGA-based video processing applications with CAL

Abstract

This article describes a pipeline synthesis and optimization technique that increases data throughput of FPGAbased system using minimum pipeline resources. The technique is applied on CAL dataflow language, and designed based on relations, matrices, and graphs. First, the initial as-soon-as-possible (ASAP) and as-late-aspossible (ALAP) schedules, and the corresponding mobility of operators are generated. From this, operator coloring technique is used on conflict and nonconflict directed graphs using recursive functions and explicit stack mechanisms. For each feasible number of pipeline stages, a pipeline schedule with minimum total register width is taken as an optimal coloring, which is then automatically transformed to a description in CAL. The generated pipelined CAL descriptions are finally synthesized to hardware description languages for FPGA implementation. Experimental results of three video processing applications demonstrate up to 3.9× higher throughput for pipelined compared to non-pipelined implementations, and average total pipeline register width reduction of up to 39.6 and 49.9% between the optimal, and ASAP and ALAP pipeline schedules, respectively.

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

“…The pipeline optimization model [34] is based on precise mathematical formulation of the optimization problem which uses the coloring of vertices of an operator conflict directed graph and an explicit stack mechanism for optimal solution search. > REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 3…”

“…A search with bounding functions is branch and bound (BB) search. In [34] a DFSBB technique for optimization of pipeline schedules was proposed. In this paper a LCSBB technique, which overcomes DFSBB with respect to pipeline quality and optimization tool throughput, is proposed.…”

“…The Bayer filter test bench was considered in detail in [34]. It contains 13 input tokens, 5 output tokens and 63 local variables, totally 81 variables.…”

“…The design critical path length is 15.62 or 25.1% over the total operator delay. As reported in [34], pipelines with 2 to 7 stages were optimized by DFSBB and synthesized to FPGAs. The global optimum was obtained for 2 and 3 stage pipelines and suboptimal solutions were generated for 4 up to 7 stage pipelines.…”

FPGA-GPU communicating through PCIe

“…For this application FPGA would be perfect for the genome decompression, while the GPU could ease the comparison process. Finally, we can mention ongoing work on the CAL language [7]. CAL, for CAL Actor Language allows the development of applications following a dataflow paradigm.…”