Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay

Staschulat, Jan; Schliecker, Simon; Ernst, Rolf

doi:10.1109/ecrts.2005.26

Cited by 87 publications

(73 citation statements)

References 9 publications

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“…SymTA/P considers the cache behavior of the preempted and preempting task to compute the maximum cache related preemption delay. This delay is considered in cache-aware response time analysis [SE04] [SSE05].…”

Section: Employed Methodsmentioning

confidence: 99%

See 1 more Smart Citation

The worst-case execution-time problem—overview of methods and survey of tools

Wilhelm

Engblom²,

Ermedahl

et al. 2008

ACM Trans. Embed. Comput. Syst.

1,457

1,029

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Abstract. The determination of upper bounds on execution times, commonly called WorstCase Execution Times (WCETs), is a necessary step in the development and validation process for hard real-time systems. This problem is hard if the underlying processor architecture has components such as caches, pipelines, branch prediction, and other speculative components. This article describes different approaches to this problem and surveys several commercially available tools and research prototypes.

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Section: Employed Methodsmentioning

confidence: 99%

“…A new scheduling approach considering the combination of timing analysis and preemptive scheduling will have to be developed. SymTA/P provides an integration of WCET calculation and cacherelated preemption delay for schedulability analysis [SSE05].…”

Section: Remaining Problems and Future Perspectivesmentioning

confidence: 99%

The worst-case execution-time problem—overview of methods and survey of tools

Wilhelm

Engblom²,

Ermedahl

et al. 2008

ACM Trans. Embed. Comput. Syst.

1,457

1,029

View full text Add to dashboard Cite

show abstract

“…The crudest approach to CRPD analysis is to assume that every preemption causes a complete flush of the entire cache; a safe but often imprecise assumption. Successively more precise estimates have been achieved by researchers [Busquets-Mataix et al 1996;Lee et al 1998;Staschulat et al 2005;Tan and Mooney 2007;Altmeyer and Maiza 2010;Altmeyer et al 2011;2012]. Estimates are generated by examining which cache blocks are definitely reused by lower-priority tasks (useful cache blocks) and which cache blocks are accessed by higher-priority tasks (evicted cache blocks).…”

Section: Real-time Systems Sharing the Cachementioning

confidence: 99%

Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

Whitham

Audsley

Davis

2014

ACM Trans. Embed. Comput. Syst.

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We describe and evaluate explicit reservation of cache memory to reduce the cache-related preemption delay (CRPD) observed when tasks share a cache in a preemptive multitasking hard real-time system. We demonstrate the approach using measurements obtained from a hardware prototype, and present schedulability analyses for systems that share a cache by explicit reservation. These analyses form the basis for a series of experiments to further evaluate the approach. We find that explicit reservation is most useful for larger task sets with high utilization. Some task sets cannot be scheduled with a conventional cache, but are schedulable with explicit reservation.

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“…This can be avoided in many embedded processors that support cachebypass load instructions. In the absence of bypass support, such evictions can be modeled in static cache analysis to bound WCETs and cache-related preemption delays [9], [15], [19]- [21]. Nonetheless, any memory access requires bus bandwidth.…”

Section: B Software-assisted Predictable Refreshmentioning

confidence: 99%

Making DRAM refresh predictable

Bhat

Mueller

2011

Real-Time Syst

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Abstract-Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Schedulability theory can assure deadlines for a given task set when periods and worst-case execution times (WCETs) of tasks are known. While periods are generally derived from the problem specification, a task's code needs to be statically analyzed to derive safe and tight bounds on its WCET. Such static timing analysis abstracts from program input and considers loop bounds and architectural features, such as pipelining and caching. However, unpredictability due to dynamic memory (DRAM) refresh cannot be accounted for by such analysis, which limits its applicability to systems with static memory (SRAM).In this paper, we assess the impact of DRAM refresh on task execution times and demonstrate how predictability is adversely affected leading to unsafe hard real-time system design. We subsequently contribute a novel and effective approach to overcome this problem through software-initiated DRAM refresh. We develop (1) a pure software and (2) a hybrid hardware/software refresh scheme. Both schemes provide predictable timings and fully replace the classical hardware autorefresh. We discuss implementation details based on this design for multiple concrete embedded platforms and experimentally assess the benefits of different schemes on these platforms. The resulting predictable execution behavior in the presence of DRAM refresh combined with the additional benefit of reduced access delays is unprecedented, to the best of our knowledge.

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Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay

Cited by 87 publications

References 9 publications

The worst-case execution-time problem—overview of methods and survey of tools

The worst-case execution-time problem—overview of methods and survey of tools

Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

Making DRAM refresh predictable

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