Scan chain diagnosis using IDDQ current measurement

Hirase, J.; Shindou, Naoki; Akahori, Koji

doi:10.1109/ats.1999.810744

Cited by 27 publications

(15 citation statements)

References 1 publication

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“…It is reported that the amount of die area consumed by scan chains and scan control signals can range from 15% to 30% [1]. Moreover, scan chain failure can account for almost 50% of chip failures [2]. Therefore, rapidly identify root causes of failures is vital to guide the failure analysis process for yield improvement.…”

Section: Introductionmentioning

confidence: 99%

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Adaptive Diagnostic Pattern Generation for Scan Chains

Wang

2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

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Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, a SAT-based technique is proposed to adaptively generate patterns to diagnose stuck-at faults in scan chains. Experimental results on ISCAS'89 benchmark circuits show that the proposed method can dramatically reduce the number of diagnostic patterns while obtain high diagnosis resolution.

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Section: Introductionmentioning

confidence: 99%

“…In the category of the tester-based solutions, people use PFA (Physical Failure Analysis) equipments to observe defective responses at different locations to identify a failing scan cell [2][3].…”

Section: Introductionmentioning

confidence: 99%

Adaptive Diagnostic Pattern Generation for Scan Chains

Wang

2008

4th IEEE International Symposium on Electronic Design, Test and Applications (Delta 2008)

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“…The other is software-based technique, which does not need any modification to the scan chain hardware, but regards the diagnosis as a sequence of guessing and verifying process [1][6] [7][8] [9] [10]. In this paper, we will focus on the hardware-based technique for diagnosing faulty scan chains.…”

Section: Introductionmentioning

confidence: 99%

Efficient diagnosis of scan chains with single stuck-at faults

Chi

Tseng

Yang

2009

2009 43rd Annual Conference on Information Sciences and Systems

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Locating the scan chain fault is a critical step for IC manufacturers to analyze failure for yield improvement. In this paper, we propose a diagnosis scheme to locate the single stuck-at fault in scan chains. Our diagnosis scheme is an improved design to a previously proposed scheme which can diagnose the output of each cell flipflop in the scan chain. With our scheme, not only the output of each cell flip-flop can be diagnosed, but also the inverse output of each cell flip-flop and the serial input of the scan chain as well. Our proposed diagnosis scheme is efficient and takes (4n+6) clock cycles in the worst case for an n-bit scan chain.

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“…These diagnosis methods can be classified into three categories. The first category is tester-based diagnosis techniques [5], [8], [9], [15], [18]. These use testers to collect diagnosis information during the loading/unloading of scan cells.…”

Section: Introductionmentioning

confidence: 99%

Utilizing Circuit Structure for Scan Chain Diagnosis

Hsieh

Lan

et al. 2014

IEEE Trans. VLSI Syst.

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Scan chain diagnosis has become a critical issue to yield loss in modern technology. In this paper, we present a scan chain partitioning algorithm and a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. In our scan chain partition algorithm, we take into consideration not only logic dependency but also the controllability between scan flip-flops. After the partition step, the ordering of scan cells is performed to decrease the range of suspect faulty scan cells by a bipartite matching reordering algorithm. The experimental results show that our method can reduce the number of suspect scan cells from 378-31 to at most 3 for most cases of ITC'99 benchmarks.Index Terms-Design for testability, digital circuits, fault diagnosis.

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Scan chain diagnosis using IDDQ current measurement

Cited by 27 publications

References 1 publication

Adaptive Diagnostic Pattern Generation for Scan Chains

Adaptive Diagnostic Pattern Generation for Scan Chains

Efficient diagnosis of scan chains with single stuck-at faults

Utilizing Circuit Structure for Scan Chain Diagnosis

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