Utilizing Circuit Structure for Scan Chain Diagnosis

Abstract

Scan chain diagnosis has become a critical issue to yield loss in modern technology. In this paper, we present a scan chain partitioning algorithm and a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. In our scan chain partition algorithm, we take into consideration not only logic dependency but also the controllability between scan flip-flops. After the partition step, the ordering of scan cells is performed to decrease the range of suspect faulty scan cells by a bipartite matching reordering algorithm. The experimental results show that our method can reduce the number of suspect scan cells from 378-31 to at most 3 for most cases of ITC'99 benchmarks.Index Terms-Design for testability, digital circuits, fault diagnosis.

Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

“…The concept of a sensitive cell has been studied previously. Scan-chain reordering [36,37] and stitching [38] have been proposed to consider logic dependency and controllability between scan cells, where scan-chain diagnosis was improved using a circuit structure. In particular, using the fan-in and fan-out dependencies between scan cells, these methods distributed sensitive cells to other chains, thereby obtaining more clues from failure logs.…”