Scan-based transition fault testing - implementation and low cost test challenges

Saxena, J.; Butler, K.M.; Gatt, J.; Raghuraman, R.; Kumar, Sahu Pratap; Basu, Sayantani; Campbell, David; Berech, J.

doi:10.1109/test.2002.1041869

Cited by 109 publications

(34 citation statements)

References 9 publications

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“…However, the detection of this fault may necessitate output capture earlier than the designated clock frequency of the digital circuit. This problem is similar to transition fault testing and several early capture methods have been developed [17].…”

Section: Propagation Of Fault Effectsmentioning

confidence: 99%

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown

Carter

Ozev

Sorin

Design, Automation and Test in Europe

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Section: Propagation Of Fault Effectsmentioning

confidence: 99%

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown

Carter

Ozev

Sorin

Design, Automation and Test in Europe

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“…In the LOS approach, higher fault coverage can be achieved relative to the broad-side approach with smaller number of test patterns. The broad-side approach, however, is more commonly used because of the well-known scan-enable signal skew problem [16,17]. This problem makes physical implementation much more difficult in aging monitoring where faster-than-at-speed test is required.…”

Section: Related Workmentioning

confidence: 99%

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

Yi¹

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-onchip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.

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“…Although the patterns that were short-listed had a lot of switching activity, many of the faults may not necessarily be unique to them. By performing fault simulation on the LS-TDF 1 pattern set, we can determine how many faults have been omitted by the short-listing as summarized in Equation 3.…”

Section: Low-switching Tdf Atpgmentioning

confidence: 99%

LS-TDF: Low-Switching Transition Delay Fault Pattern Generation

Lee

Tehranipoor

2008

26th IEEE VLSI Test Symposium (Vts 2008)

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Abstract-Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring these chips operate at the specified frequency. However, current industrially used X-filling (random-fill or compression) schemes tend to generate transition delay fault patterns with switching activity much higher than what would be seen during functional mode operation of the chip, potentially causing failures that would not occur in the field. In this paper, we present a lowswitching transition delay fault pattern generation flow. The flow short-lists patterns based on high switching activity, which is determined by the fault lists of each pattern. Once those patterns with high switching are filtered, they will be replaced by low-switching patterns to recover any lost fault coverage. The proposed pattern generation flow works well with commercial tools and can easily be integrated into an industrial flow.

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Scan-based transition fault testing - implementation and low cost test challenges

Cited by 109 publications

References 9 publications

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown

An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring

LS-TDF: Low-Switching Transition Delay Fault Pattern Generation

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