2019 IEEE 11th International Memory Workshop (IMW) 2019
DOI: 10.1109/imw.2019.8739270
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Scaling Split-Gate Flash Memory Technology for Advanced MCU and Emerging Applications

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Cited by 4 publications
(2 citation statements)
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“…The SSI mechanism is investigated systematically by means of Synopsys Sentaurus technology computer-aided design (TCAD) simulations, varying the program conditions. All the numerical simulations have been performed fixing the values of the coupling gate voltage (V CG ), bit line voltage (V BL ) and erase gate voltage (V EG ) reported in literature [19][20][21][22][23] for the latest technology node, listed in Table 1 and shown in Figure 2. In particular, the bias conditions are: V CG = HV (>10 V) [19][20][21][22]; word line and commons source voltages (V WL and V CS , respectively) have been varied, respectively, in the range 0.7-1.1 V and 4-4.6 V [20,21,23]; V EG = V CS in order to avoid charge migration between the two electrodes [23]; I BL is fixed at~1 µA [20,24].…”
Section: Methodsmentioning
confidence: 99%
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“…The SSI mechanism is investigated systematically by means of Synopsys Sentaurus technology computer-aided design (TCAD) simulations, varying the program conditions. All the numerical simulations have been performed fixing the values of the coupling gate voltage (V CG ), bit line voltage (V BL ) and erase gate voltage (V EG ) reported in literature [19][20][21][22][23] for the latest technology node, listed in Table 1 and shown in Figure 2. In particular, the bias conditions are: V CG = HV (>10 V) [19][20][21][22]; word line and commons source voltages (V WL and V CS , respectively) have been varied, respectively, in the range 0.7-1.1 V and 4-4.6 V [20,21,23]; V EG = V CS in order to avoid charge migration between the two electrodes [23]; I BL is fixed at~1 µA [20,24].…”
Section: Methodsmentioning
confidence: 99%
“…In all the simulations, a single 1 s-long pulse is applied on all the electrodes. [19][20][21][22][23].…”
Section: Methodsmentioning
confidence: 99%