Scaling constraints in nanoelectronic random-access memories

Abstract

Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F(2)) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 x 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 x 512.

Multilevel Biomemory Device Consisting of Recombinant Azurin/Cytochrome c

“…[2,3] Several valuable concepts have been proposed for developing the next generation of memory devices including spin-based and ferromagnetism-based devices. [4][5][6] Over the past decade, several concepts for molecular electronics, defined as molecular-level electronic systems, that only use a few electrons for operation have been introduced. This novel electronic design has the potential to resolve the technological challenges currently facing the industry and open up new strategies for enhancing device integration density.…”

An Analytical Approach for Memristive Nanoarchitectures

“…Extensive analytical studies have been carried out in the area of nano crossbar memory design [2], [40]- [43]. Here we extend these studies and also the comprehensive analytical framework, introduced early in this section, to the simulation of the memristive and CRS-based arrays.…”

“…The cross-point element could be either a CRS device or a memristor. In order to read any stored bit in R i,j , similar to many other reported schemes [2], [40]- [42], here we apply V pu = V READ to the i th bitline, j th word-line is grounded, and all other word and bit lines are floating. A direct benefit of this approach is the pull-up resistor (R pu ) can be implemented in nano domain [41].…”

Memory Select Devices

“…One example of these sneak paths is shown in Figure 12.2. The impact of the sneak paths on the reading and writing operations of crossbar arrays has been analyzed in numerous papers [6][7][8][9][10][11][12][13][14].…”