Scaling challenges of NAND flash memory and hybrid memory system with storage class memory &amp;amp; NAND flash memory

Takeuchi, Ken

doi:10.1109/cicc.2013.6658450

Cited by 12 publications

(2 citation statements)

References 5 publications

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“…The intersection of a control gate plate with a pillar identifies a single memory cell; each string is connected to a bitline through an upper select transistor (BLS). The bottom of the Bit density can be increased by adding more control gate plates [10,11], while the number of the critical lithography steps remains constant because the whole stack of control gates is completely punched through with one lithography step only. It is worth highlighting the fact that the body of the vertical transistor is completely made of polysilicon; in fact, the aspect ratio of the punched hole is so high that it becomes almost impossible to achieve good production yield without non-selective deposition process steps.…”

Section: Bicsmentioning

confidence: 99%

3D Charge Trap NAND Flash Memories

Crippa¹,

Micheloni²

2016

3D Flash Memories

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Section: Bicsmentioning

confidence: 99%

3D Charge Trap NAND Flash Memories

Crippa¹,

Micheloni²

2016

3D Flash Memories

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“…As the CMOS technology scales down to the 22-nm node, conventional memories are confronted with scalability problem [9], [10]. Thus, the STT-RAM with great scalability is widely researched as a next-generation memory.…”

Section: Introductionmentioning

confidence: 99%

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM

Song

Kim

et al. 2015

IEEE Trans. Circuits Syst. I

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As technology node shrinks, spin-transfer-torque random access memory (STT-RAM) has become a promising memory solution owing to its great scalability. However, the increase in process variation and decrease in the supply voltage result in the degradation of the read yield; thus, achieving the target read yield is an important issue in a deep-submicrometer technology node. In this paper, we propose a latch offset cancellation sense amplifier (LOC-SA) that cancels the latch offset with a compact area by merging the sensing circuit, latch sense amplifier, and write driver. By virtue of the latch offset cancellation characteristic, the voltage developing time can be significantly saved, leading to sensing-speed improvement. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the LOC-SA satisfies a target read yield of six-sigma (96.74% for 32 Mb) with more than 2 faster sensing speed, 1.12 lower read energy, and 1.13 smaller area when compared with the best value of design parameters of other sense amplifiers.Index Terms-Latch sense amplifier, MRAM, offset cancellation technique, read access pass yield, STT-RAM.

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