Scalable transformer model based on ladder topological equivalent circuit for Si RFICs

Abstract

Scalable modeling methodology of on-chip spiral interleaved transformer is proposed. The novel equivalent circuit based on ladder topology is composed of lumped elements and their parameters are completely derived from the physical structure. The circuit topology enables to express the inductive and capacitive coupling effect between half turn segmented wires accurately. The circuit also contributes to obtain the scalability related to wire width/space, length, and diameter. In this model, coupling capacitance between adjacent wires is given by considering parallel paths through oxide layer and Si substrate. The model simulation result matched the measurement result of a fabricated transformer TEG with the error less than 5% for wide frequency range upto quasi-millimeter wave band.

An equivalent lumped circuit model for on-chip helical transformers

“…As the integrated circuits technologies advance, more metal layers are available for the design of multilayer inductors, and make it possible that the devices can be more compact. As one of the most important work, the modeling of planner transformers drew much research effort [1,2]. However, because of their complexity and diversity, the modeling of multilayer transformers is not that easy.…”

A lumped element circuit model for monolithic transformers in silicon-based RFICs

“…For first-pass circuit design and reliable circuit simulations, accurate lumpedelement circuit models for on-chip transformers are important. To this end, various transformer topologies have been proposed and studied and several models along with their extraction procedures have been developed in recent years (e.g., [1][2][3][4]). …”

“…Reference [1] presents a monolithic transformer with a 24 sided concave-convex geometry while [2] discusses a model for on-chip spiral interleaved transformer using a ladder topology of lumped elements. Reference [3] gives a review of the electrical performance of on-chip transformers and presents the characteristics of two-port and multi-port transformers.…”

Node Failures and Space Complexity Variations in Step Topology under Distributed Environment

“…Zaidi and Saxena [9] have also studied link failures and bypass link failures in the Mobile Adhoc Network (MANET) which is arranged through step topology and allocation of resources are also described by the use of UML. The ladder topology is well defined in the reference [10]. Description on Miniaturized transmission lines based on hybrid lattice-ladder topology is available in [11].…”