Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

Abstract

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Effects of the surface charge screening and temperature on the vortex domain patterns of ferroelectric nanodots

“…[1][2][3][4][5][6][7] Particularly, due to effects of size, surface, and interface, ferroelectric nanostructures may be quite different in property from their bulk counterparts. [8][9][10][11][12][13] The small size, high surface-volume ratio, and inherent functional properties of ferroelectric nanostructures are important in developing functional nanodevices and device miniaturization.…”

Charge gradient microscopy

“…screen charge | atomic force microscopy | piezoresponse | charge scraping F erroelectric and piezoelectric materials have attracted great attention due to their applications in commercial markets such as a medical imaging (1-3), next generation inkjet printer heads (4), precision-positioning stages (5,6), fuel injectors in diesel engines (7,8), and memory devices (9,10). The macroscopic properties of ferroelectric and piezoelectric materials that make them appealing for current and future technologies can be more fully understood and improved through detailed knowledge of their domain structures at the nanoscale and mesoscale (11)(12)(13)(14)(15).…”

Printed Organic Circuits for Reading Ferroelectric Rewritable Memory Capacitors

“…1 is designed for discriminating between memory states of an organic FE capacitor C FE using the switching voltage of 20 V. The memory bitline V bl is connected to the gate of a common-source gain stage, comprising OTFT M1 and resistor R. M2 is for zeroing the read circuit and M3 allows for writing the memory cell [9] and is switched OFF in the readout process. V CBL is gate voltage to M3 to control the memory bitline voltage.…”