Scalable parallel processing for H.264 encoding application to multi/many-core processor

Takeuchi, Yujiro; Nakata, Yoshio; Kawaguchi, Hiroshi; Yoshimoto, Masahiko

doi:10.1109/icicip.2010.5565292

Cited by 5 publications

(5 citation statements)

References 6 publications

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“…In fact, Wang et al [27] proposed an MB level parallelism (MBLP), where each MB is processed on distinct CPU. Takeuchi et al [28] choose an MB line level partitioning (MBLLP) where each image is composed by MBL and each MBL is performed on separate CPU. MBLP and MBLLP engender interesting solutions in terms of reducing data loading latency because of their small data granularity.…”

Section: Related Workmentioning

confidence: 99%

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture

Belhadj

Bahri

Marrakchi

et al. 2015

IET Computers & Digital Techniques

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Section: Related Workmentioning

confidence: 99%

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture

Belhadj

Bahri

Marrakchi

et al. 2015

IET Computers & Digital Techniques

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“…The third data structure used for the parallel processing of H.264/AVC is slice level parallelism (SLP). This partitioning consists in dividing the frame into independent slices (Takeuchi, 2010); this partitioning is allowed by the H.264/AVC standard. Each slice is treated by one CPU.…”

Section: Related Work For H264/avc Parallelismmentioning

confidence: 99%

MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder

Belhadj

Marrakchi²,

Ayed

et al. 2014

International Journal of Embedded and Real-Time Communication Systems

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Using multiprocessor technology is an interesting solution for reducing the processing time of complex video encoders such as H.264/Advanced Video Coding (AVC). This paper details different levels of parallelism presented in related works for H.264/AVC encoder. An efficient Macro Blocks Line level parallelism for the intra prediction encoding chain of H.264/AVC for High Definition (HD) video is proposed. It is implemented on MPSoC architecture using an open and free platform for virtual prototyping named SoCLib. Comparing to related works, the proposed partitioning meets strongly the size of required memory constraint and provides an interesting speed-up. The proposed architecture is based on three processors and ensures a reduced circuit area. Experimental results reveal a run time saving of about 59.8% in terms of processing speed, compared to a classical execution based on a single CPU, without affecting the quality of the reconstructed video. Using multiprocessor technology is an interesting solution for reducing the processing time of complex video encoders such as H.264/Advanced Video Coding (AVC). This paper details different levels of parallelism presented in related works for H.264/AVC encoder. An efficient Macro Blocks Line level parallelism for the intra prediction encoding chain of H.264/AVC for High Definition (HD) video is proposed. It is implemented on MPSoC architecture using an open and free platform for virtual prototyping named SoCLib. Comparing to related works, the proposed partitioning meets strongly the size of required memory constraint and provides an interesting speed-up. The proposed architecture is based on three processors and ensures a reduced circuit area. Experimental results reveal a run time saving of about 59.8% in terms of processing speed, compared to a classical execution based on a single CPU, without affecting the quality of the reconstructed video.

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“…Fortunately, the Tilera's platform supports a broad range of possibilities. See, for example [6], which explores several alternatives for the H.264 encoder.…”

Section: Encoder Parallelizationmentioning

confidence: 99%