MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder

Abstract

Using multiprocessor technology is an interesting solution for reducing the processing time of complex video encoders such as H.264/Advanced Video Coding (AVC). This paper details different levels of parallelism presented in related works for H.264/AVC encoder. An efficient Macro Blocks Line level parallelism for the intra prediction encoding chain of H.264/AVC for High Definition (HD) video is proposed. It is implemented on MPSoC architecture using an open and free platform for virtual prototyping named SoCLib. Comparing to related works, the proposed partitioning meets strongly the size of required memory constraint and provides an interesting speed-up. The proposed architecture is based on three processors and ensures a reduced circuit area. Experimental results reveal a run time saving of about 59.8% in terms of processing speed, compared to a classical execution based on a single CPU, without affecting the quality of the reconstructed video. Using multiprocessor technology is an interesting solution for reducing the processing time of complex video encoders such as H.264/Advanced Video Coding (AVC). This paper details different levels of parallelism presented in related works for H.264/AVC encoder. An efficient Macro Blocks Line level parallelism for the intra prediction encoding chain of H.264/AVC for High Definition (HD) video is proposed. It is implemented on MPSoC architecture using an open and free platform for virtual prototyping named SoCLib. Comparing to related works, the proposed partitioning meets strongly the size of required memory constraint and provides an interesting speed-up. The proposed architecture is based on three processors and ensures a reduced circuit area. Experimental results reveal a run time saving of about 59.8% in terms of processing speed, compared to a classical execution based on a single CPU, without affecting the quality of the reconstructed video.