Scalable Parallel Memory Architectures for Video Coding

Tanskanen, Jarno M. A.; Niittylahti, J.

doi:10.1023/b:vlsi.0000040428.04740.fe

Cited by 12 publications

(13 citation statements)

References 16 publications

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“…Another Tanskanen_s parallel memory system specialized for video coding is implemented in [59] and [60]. The evaluated three-slot VLIW DSP core allows one arithmetic operation and two simultaneous data access operations to two data memories [60].…”

Section: Evaluated Parallel Memory Implementationsmentioning

confidence: 99%

Configurable Data Memory for Multimedia Processing

Aho

Vanne

Hämäläinen

2007

J Sign Process Syst Sign Image

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In modern multimedia applications, memory bottleneck can be alleviated with special stride data accesses. Data elements in stride access can be retrieved in parallel with parallel memories, in which the idea is to increase memory bandwidth with several memory modules working in parallel and feed the processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the accessed data element count equals to the number of memory modules. Timing and area estimates are given for Altera Stratix FPGA and 0.18 micrometer CMOS process with memory module count from 2 to 32. The FPGA results show 129 MHz clock frequency for a system with 16 memory modules when read and write latencies are 3 and 2 clock cycles, respectively. The complexity of the proposed system is shown to be a trade-off between application specific and highly configurable parallel memory system.

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Section: Evaluated Parallel Memory Implementationsmentioning

confidence: 99%

Configurable Data Memory for Multimedia Processing

Aho

Vanne

Hämäläinen

2007

J Sign Process Syst Sign Image

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“…So the data (x,y) are located at the a(x,y) position of the SRAM s(x,y) . The bank address generator and the memory access logic are the most powersensitive circuits in the 2D memory [3], so our main work is to reduce the power consumptions resulting from them.…”

Section: Motivationmentioning

confidence: 99%

“…However, the power consumption restricts the usage of the 2D memory in vector DSPs [3]. We propose a Low-Power 2D memory (LP2D) according to the memory access features of the sliding-window applications.…”

mentioning

confidence: 99%

“…When mapped on a vector DSP with the 1D memory, these applications will suffer the performance degradation resulting from irregular data accesses. The 2D memory [3,4,5,6], that uses the 'X' and 'Y' coordinates to denote the memory space, can keep the 2D relation among pixels steady and support conflict-free block accesses, thus increasing the data reutilization and improve the performance of sliding-window applications.…”

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confidence: 99%

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LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs

Liu

Chen

Ning

et al. 2011

IEICE Electron. Express

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Abstract:The power consumption of the 2D memory restricts its usage in vector DSPs for sliding-window applications with irregular memory accesses. This paper introduces a novel Low-Power 2D memory (LP2D), which can effectively reduce the power consumption to the traditional 2D memory without sacrificing its performance. By the theory analysis, we design an adjacent address checker which can generate the bank control mask to turn off some power-sensitive circuits of the 2D memory. Experimental results show that the LP2D can reduce the power consumption by 31.7%∼62.9% with less than 1.3% additional hardware cost, as compared with the traditional 2D memory schemes.

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“…Most of the computations use regular and repetitive data accesses. For example, the memory access patterns for video coding are analyzed in [6]. The data accesses tend to be data independent, meaning that the locations of the data in memory do not depend on the data values and can be determined beforehand.…”

Section: Introductionmentioning

confidence: 99%

ePUMA: A novel embedded parallel DSP platform for predictable computing

Wang

Sohl

Kraigher

et al. 2010

2010 2nd International Conference on Education Technology and Computer

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Abstract-In this paper, a novel parallel DSP platform based on master-multi-SIMD architecture is introduced. The platform is named ePUMA 1 [1]. The essential technology is to use separated data access kernels and algorithm kernels to minimize the communication overhead of parallel processing by running the two types of kernels in parallel. ePUMA platform is optimized for predictable computing. The memory subsystem design that relies on regular and predictable memory accesses can dramatically improve the performance according to benchmarking results. As a scalable parallel platform, the chip area is estimated for different number of coprocessors. The aim of ePUMA parallel platform is to achieve low power high performance embedded parallel computing with low silicon cost for communications and similar signal processing applications.

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Scalable Parallel Memory Architectures for Video Coding

Cited by 12 publications

References 16 publications

Configurable Data Memory for Multimedia Processing

Configurable Data Memory for Multimedia Processing

LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs

ePUMA: A novel embedded parallel DSP platform for predictable computing

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