Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC

Kulmala, Ari; Lehtoranta, O.; Hämäläinen, Timo D.; Hännikäinen, Marko

doi:10.1155/es/2006/38494

Cited by 14 publications

(13 citation statements)

References 5 publications

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“…Then, the measured values are compared to our previous estimations [10,8]. Last, we will extend our estimation based on the new findings.…”

Section: Performance Scalabilitymentioning

confidence: 91%

“…Different aspects and configurations of the MPSoC architecture have been thoroughly studied in our past work [10,[25][26][27][28][29][30]8]. Main objectives, findings, and significance with respect to this paper are summarized in Table 2.…”

Section: Mpsoc Architecture On Fpgamentioning

confidence: 99%

“…Based on the study [8], two hardware accelerators have been designed and implemented. DQ component gets the required data from the CPU, whereas the ME fetches data from the SDRAM directly.…”

Section: Hardware Acceleratorsmentioning

confidence: 99%

“…Our parallel video encoder software is based on horizontal spatial parallelization [8]. Briefly, the application consists of a master CPU (Nios) that controls the encoding flow, collects the bitstream, and handles the I/O, such as sending data back and forth with a PC via Ethernet.…”

Section: Mpeg-simple Profile Applicationmentioning

confidence: 99%

“…However, our approach is substantially different because instead of raw performance, we have opted for maximum flexibility and upgradeability as well as technology and device independency. We use highly scalable data parallel processing method [8] instead of poorly scalable functional parallelism. Our architecture allows rapid upgrade to different encoding standards and effortless changes in the architecture.…”

mentioning

confidence: 99%

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This paper shows how a bus topology performs as a System-on-Chip (SoC) interconnection. We measure and analyze Heterogeneous IP Block Interconnection (HIBI) bus for a multiple clock domain, Multiprocessor System-on-Chip (MPSoC) with an MPEG-4 video encoding application on FPGA. The studied MPSoC contains up to 22 IP blocks: 11 soft processors, 8 hardware accelerators and three other components. A novel approach of frequency scaling is used to isolate the impact of various architecture components. The system is benchmarked in various configurations. For example, HIBI is run at 100× speed with respect to processors to resemble ideal interconnection. Based on the measurements with up to 16.9frames/s CIF (352 × 288) encoding speed, estimation for HDTV resolution video encoder is presented. The required optimizations are discussed. Finally, it is shown that 25frames/s 1280 × 720 video encoder needs 55 MHz HIBI but 670 MHz general-purpose soft RISC processors. In practice, the processing performance has to be boosted by implementing hardware acceleration and improving memory hierarchy. Clearly, HIBI is not the limiting factor.

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“…Then, the measured values are compared to our previous estimations [10,8]. Last, we will extend our estimation based on the new findings.…”

Section: Performance Scalabilitymentioning

confidence: 91%