Scalable model for predicting the effect of negative bias temperature instability for reliable design

Bhardwaj, Sarvesh; Wang, Wenping; Vattikonda, Rakesh; Cao, Yu; Vrudhula, Sarma

doi:10.1049/iet-cds:20070225

Cited by 38 publications

(25 citation statements)

References 8 publications

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“…If the circuit time delay is expressed as (1), the NBTI, considering the process variation, increases not only the mean time delay (d t=0 ) of the circuit, but also the standard deviation (σ total,t=0 =√Σd 2 t=0,i ) [18]. As shown in Table 1, change of the threshold voltage by T ox increased by about 2% when compared with the same change utilizing the conventional long-term model [19]. The effect of V th0 was 0.5%, smaller than that of T ox .…”

Section: The Variability On Circuit Degradationmentioning

confidence: 99%

See 1 more Smart Citation

Timing Analysis Techniques Review for sub-30 nm Circuit Designs

Kim

Han²,

Jewell³

2010

JSTS:Journal of Semiconductor Technology and Science

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Abstract-With scaled technology, timing analysis of circuits becomes more and more difficult. In this paper, we review recently developed circuit simulation techniques created to deal with the cost issues of transistor-level simulations. Various techniques for fast SPICE simulations and Monte Carlo simulations are introduced. Moreover, process and aging variation issues are mentioned, along with promising methodologies.

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Section: The Variability On Circuit Degradationmentioning

confidence: 99%

“…It increases the threshold voltage (V th ) of PMOS over time, causing alterations in circuit performance, including time delays. Various studies have been carried out to minimize the effect of NBTI the circuits, specifically regarding modeling, analysis, and design techniques of NBTI [19][20][21][22].…”

Section: The Variability On Circuit Degradationmentioning

confidence: 99%

Timing Analysis Techniques Review for sub-30 nm Circuit Designs

Kim

Han²,

Jewell³

2010

JSTS:Journal of Semiconductor Technology and Science

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“…The cumulative aging-induced shift in threshold voltage from time 0 up to the beginning of time-step i is denoted as V IT(i) . The increase in interface traps, N IT , leads to a linear shift in threshold voltage [18]. Hence (8) where N IT(i) is the amount of interface traps accumulated from time 0 up to the beginning of time-step i, q is the elementary charge, and C ox is the gate-oxide capacitance.…”

Section: E Threshold Voltagementioning

confidence: 99%

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-stateaging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-timeaging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.Index Terms-Adaptive supply voltage and clock frequency, circuit aging, energy-efficiency, lifetime reliability.

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“…For example, Bhardwaj et al suggested a long-term model that accounts for the stress/recovery phase by using a duty cycle (α) (1) [1]. …”

Section: Introductionmentioning

confidence: 99%

“…In recent NBTI-related work, the duty cycle (α) and T clk have been used to account for the stress/recovery phenomenon of the NBTI [1][2][3]. The duty cycle represents the ratio between the on and the off time of the PMOS and can be calculated for each transistor in a circuit as follows:…”

Section: Introductionmentioning

confidence: 99%

An Accurate Gate-level Stress Estimation for NBTI

Han¹,

Lee

Kim³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Negative bias temperature instability (NBTI) has become a major factor determining circuit reliability. The effect of the NBTI on the circuit performance depends on the duty cycle which represents the stress and recovery conditions of each device in a circuit. In this paper, we propose an analytical model to perform more accurate duty cycle estimation at the gate-level. The proposed model allows accurate (average error rate: 3%) computation of the duty cycle without the need for expensive transistor-level simulations Furthermore, our model estimates the waveforms at each node, allowing various aging effects to be applied for a reliable gatelevel circuit aging analysis framework

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Scalable model for predicting the effect of negative bias temperature instability for reliable design

Cited by 38 publications

References 8 publications

Timing Analysis Techniques Review for sub-30 nm Circuit Designs

Timing Analysis Techniques Review for sub-30 nm Circuit Designs

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

An Accurate Gate-level Stress Estimation for NBTI

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