Scalable high performance main memory system using phase-change memory technology

Abstract

The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. An alternative memory technology that uses resistance contrast in phase-change materials is being actively investigated in the circuits community. Phase Change Memory (PCM) devices offer more density relative to DRAM, and can help increase main memory capacity of future systems while remaining within the cost and power constraints. In this paper, we analyze a PCM-based hybrid main memory system using an architecture level model of PCM.We explore the trade-offs for a main memory system consisting of PCMstorage coupled with a small DRAM buffer. Such an architecture has the latency benefits of DRAM and the capacity benefits of PCM. Our evaluations for a baseline system of 16-cores with 8GB DRAM show that, on average, PCM can reduce page faults by 5X and provide a speedup of 3X. As PCM is projected to have limited write endurance, we also propose simple organizational and management solutions of the hybrid memory that reduces the write traffic to PCM, boosting its lifetime from 3 years to 9.7 years.

Loose-Ordering Consistency for persistent memory

“…The average overhead of a clflush and mfence combined together is reported to be 250ns [14], which makes this approach costly, given that persistent memory access times are expected to be on the order of tens to hundreds of nanoseconds [3,4,7]. 1 The two instructions flush dirty data blocks from the CPU cache to persistent memory and wait for the completeness of all memory writes, and incur high overhead in persistent memory [10,14,32,33].…”

“…Since these technologies have low idle power, high storage density, and good scalability properties compared to DRAM [1,2], they have been regarded as potential alternatives to replace or complement DRAM as the technology used to build main memory [3,4,5,6,7,8,9]. Perhaps even more importantly, the non-volatility property of these emerging technologies promises to enable memory-level storage (i.e., persistent memory), which can store data persistently at the main memory level at low latency [10,11,12,13,14,15,16].…”

“…Therefore, in order to preserve persistence ordering from the CPU cache to persistent memory, software needs to explicitly include the relatively costly cache flush (e.g., clflush) and memory fence (e.g., mfence) instructions (at the end of each transaction) to force the ordering of cache writebacks [11,13,14,15]. The average overhead of a clflush and mfence combined together is reported to be 250ns [14], which makes this approach costly, given that persistent memory access times are expected to be on the order of tens to hundreds of nanoseconds [3,4,7].…”

“…Their DRAM-comparable performance and better-than-DRAM technology-scalability, which can enable high memory capacity at low cost, make these technologies promising alternatives to DRAM [3,4,5]. As such, many recent works examined the use of these technologies as part of main memory [3,4,5,6,7,8,9,10,11,12,13,14,15,16], providing disk-like data persistence at DRAM-like latencies.…”

Understanding the Impact of BPRAM on Incremental Checkpoint

“…Second, it is a persistent storage like disk and flash, and up to four orders of magnitude faster than flash [20]- [23]. According to recent research, the read latency of PCM can be as fast as 10 ns [24] and the write latency can be as fast as 100 ns [22]. As demonstrated by Condit et al [25], PCM DIMM has high capacity and operates in the same way like DRAM DIMM.…”