Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression

Abstract

Hyperspectral data processing is a computationally intensive task that is usually performed in high-performance computing clusters. However, in remote sensing scenarios, where communications are expensive, a compression stage is required at the edge of data acquisition before transmitting information to ground stations for further processing. Moreover, hyperspectral image compressors need to meet minimum performance and energy-efficiency levels to cope with the real-time requirements imposed by the sensors and the available power budget. Hence, they are usually implemented as dedicated hardware accelerators in expensive space-grade electronic devices. In recent years though, these devices have started to coexist with low-cost commercial alternatives in which unconventional techniques, such as run-time hardware reconfiguration are evaluated within research-oriented space missions (e.g., CubeSats). In this paper, a run-time reconfigurable implementation of a low-complexity lossless hyperspectral compressor (i.e., CCSDS 123) on a commercial off-the-shelf device is presented. The proposed approach leverages an FPGA-based on-board processing architecture with a data-parallel execution model to transparently manage a configurable number of resource-efficient hardware cores, dynamically adapting both throughput and energy efficiency. The experimental results show that this solution is competitive when compared with the current state-of-theart hyperspectral compressors and that the impact of the parallelization scheme on the compression rate is acceptable when considering the improvements in terms of performance and energy consumption. Moreover, scalability tests prove that run-time adaptation of the compression throughput and energy efficiency can be achieved by modifying the number of hardware accelerators, a feature that can be useful in space scenarios, where requirements change over time (e.g., communication bandwidth or power budget). INDEX TERMS Data compression, dynamic and partial reconfiguration, FPGAs, high-performance embedded computing, hyperspectral images, on-board processing.

Comprehensive review of hyperspectral image compression algorithms

“…Based on segmented of bands (BRSB) divides the bands in set of multiple segments using average correlation value, which is followed by BRCCBH for band reordering. Rodriguez et al 50 proposed another technique for hardware acceleration of lossless CCSDS 123 algorithm. It uses dynamic and partial reconfiguration-based architecture that manages HyLoC, a low complexity compressor core for fast and real-time compression.…”

SHyLoC 2.0: A Versatile Hardware Solution for On-Board Data and Hyperspectral Image Compression on Future Space Missions

“…Rodríguez et al propose in [34] a parallel implementation of HyLoC, previously described in this study. For this purpose, the ARTICo 3 framework is used, a hardwarebased processing architecture for high-performance embedded systems developed by some the same authors.…”

Inference in Supervised Spectral Classifiers for On-Board Hyperspectral Imaging: An Overview

“…As a result, low-power consumption architectures such as field-programmable gate array (FPGAs) [125,126] and efficient GPU architectures [110] have emerged as an alternative to transfer part of the processing from the ground segment to the remote sensing sensor. A variety of techniques have been adapted to be carried out on-board [127], ranging from pre-processing methods, such as data calibration [128], correction [129], compression [123,130] and georeferencing [131], to final user applications, for instance data unmixing [126], object detection [132] and classification [110,133]. In the context of classification, usually, the training of supervised methods should be performed offline (in external systems), so that only the trained model will be implemented in the device (which will only perform the inference operation).…”