Scalable GPU-Accelerated IPv6 Lookup Using Hierarchical Perfect Hashing

Zhou, Shijie; Prasanna, Viktor K.

doi:10.1109/glocom.2015.7417259

Cited by 6 publications

(2 citation statements)

References 19 publications

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“…Various IP lookup mechanisms have been proposed, from ternary content addressable memory (TCAM)-based schemes [7,8] to algorithms based on hash [9,10], trie [11][12][13], and Bloom filter [14,15]. However, the above algorithms are mainly intended for terrestrial networks, some could not be applied in demanding inter-satellite networks directly; for instance, the traditional TCAM possesses the characteristics of a high cost and large power consumption, and the hashing algorithm inevitably has hash collisions.…”

Section: Introductionmentioning

confidence: 99%

Cuckoo Bloom Hybrid Filter: Algorithm and Hardware Architecture for High Performance Satellite Internet Protocol Route Lookup

Zhang,

Qiao,

et al. 2023

Applied Sciences

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The next-generation satellite Internet Protocol (IP) router is required to achieve tens of millions of route lookups per second, since satellite Internet services based on low Earth orbit (LEO) constellations have become a reality. Due to the limitation of hardware resources on satellites and the high reliability requirements for equipment, a new satellite IP route lookup architecture is proposed in this paper. The proposed architecture uses a Bloom and cuckoo filter-based structure called cuckoo Bloom hybrid filter (CBHF), which guarantees only one off-chip memory access per lookup, to accelerate the Prefix-Route Trie (PR-Trie) algorithm. The proposed architecture has been evaluated through both a behavioral simulation in C++ language and a hardware implementation in Verilog hardware description language (HDL). Our simulation and implementation results show that the proposed satellite IP route lookup architecture can achieve a single-port throughput beyond 13 Gbps on a field programmable gate array (FPGA) board with a single DDR3 memory chip when operating at 200 MHz. In addition, the resource utilization in the FPGA shows that the proposed architecture also supports triple modular redundancy (TMR) to enhance reliability.

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Section: Introductionmentioning

confidence: 99%

Cuckoo Bloom Hybrid Filter: Algorithm and Hardware Architecture for High Performance Satellite Internet Protocol Route Lookup

Zhang,

Qiao,

et al. 2023

Applied Sciences

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“…Content may change prior to final publication. [45], [49]- [51], which have a similar tendency to achieve high lookup rates with large batch sizes. When considering LPM methods, it is easy to minimize the size of the routing table and the number of references to it with IPv4 because its address length is just 32-bit; however, IPv6 is not, although it is required in the practical packet processing software.…”

Section: Introductionmentioning

confidence: 99%

Fast Longest Prefix Matching by Exploiting SIMD Instructions

et al. 2020

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Longest prefix matching (LPM) is a fundamental process in IP routing used not only in traditional hardware routers but also in software middleboxes. However, the performance of LPM in software is still insufficient for processing packets at over 100 Gbps, although previous studies have tackled this issue by exploiting the CPU cache or accelerators such as GPUs. To improve the performance of software LPM further, we propose a novel LPM method called Spider, which exploits a single-instruction multiple-data (SIMD) mechanism in the CPU. Spider achieves performing LPM for up to 16 destination IP address in parallel by a routing table structure carefully designed for processing by the SIMD instructions. We evaluated Spider from the following three perspectives: the improvement of LPM performance derived from the parallelism provided by the SIMD mechanism, performance comparison with other methods, and performance scalability. The evaluation shows that Spider dramatically improves the LPM performance, which reaches 1.8-3.2 times compared with the state-of-the-art methods. Moreover, Spider achieves 5,074 million lookups per second with 16 CPU cores, which is equivalent to the processing capacity of 3.4 Tbps in short packets; the performance opens up the possibility of packet processing at the terabit-class rate by software.INDEX TERMS IP routing, longest prefix matching (LPM), single-instruction multiple-data (SIMD), software middlebox.

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