Fast Longest Prefix Matching by Exploiting SIMD Instructions

Abstract

Longest prefix matching (LPM) is a fundamental process in IP routing used not only in traditional hardware routers but also in software middleboxes. However, the performance of LPM in software is still insufficient for processing packets at over 100 Gbps, although previous studies have tackled this issue by exploiting the CPU cache or accelerators such as GPUs. To improve the performance of software LPM further, we propose a novel LPM method called Spider, which exploits a single-instruction multiple-data (SIMD) mechanism in the CPU. Spider achieves performing LPM for up to 16 destination IP address in parallel by a routing table structure carefully designed for processing by the SIMD instructions. We evaluated Spider from the following three perspectives: the improvement of LPM performance derived from the parallelism provided by the SIMD mechanism, performance comparison with other methods, and performance scalability. The evaluation shows that Spider dramatically improves the LPM performance, which reaches 1.8-3.2 times compared with the state-of-the-art methods. Moreover, Spider achieves 5,074 million lookups per second with 16 CPU cores, which is equivalent to the processing capacity of 3.4 Tbps in short packets; the performance opens up the possibility of packet processing at the terabit-class rate by software.INDEX TERMS IP routing, longest prefix matching (LPM), single-instruction multiple-data (SIMD), software middlebox.

Scalable Balanced Pipelined IPv6 Lookup Algorithm

“…Most of the lookup algorithms are designed to support IPv4 addresses, but they usually do not scale well to longer IPv6 addresses. There is an ongoing effort to develop IP lookup algorithms that achieve efficient IPv6 addresses support [2], [7], [9]- [10], [12], [14], [16], [19]- [20], [22], [25]- [26], [29]. All lookup algorithms can be classified into three main categories [2]: tree based algorithms [3]- [22], Ternary Content-Addressable Memory (TCAM) based algorithms [23]- [25], and hash based algorithms [26]- [29].…”

“…There is an ongoing effort to develop IP lookup algorithms that achieve efficient IPv6 addresses support [2], [7], [9]- [10], [12], [14], [16], [19]- [20], [22], [25]- [26], [29]. All lookup algorithms can be classified into three main categories [2]: tree based algorithms [3]- [22], Ternary Content-Addressable Memory (TCAM) based algorithms [23]- [25], and hash based algorithms [26]- [29]. We present the tree based algorithms related work in this section because BPL belongs to this category.…”

“…Many novel solutions are adjusted and tuned for specific platforms [20]- [22]. In [20], IP lookup is adjusted for Phase-Change Memory (PCM) based memory system, and in [21], the proposed IP lookup solution utilizes the Graphics Processing Unit (GPU) parallel computing.…”

“…In [20], IP lookup is adjusted for Phase-Change Memory (PCM) based memory system, and in [21], the proposed IP lookup solution utilizes the Graphics Processing Unit (GPU) parallel computing. IP lookup solution proposed in [22] exploits the Single Instruction, Multiple Data (SIMD) instructions.…”

Thermal design power and vectorized instructions behavior

“…Among the unexpected behaviors, this study provides actual examples illustrating that faster runs do not necessarily imply less energy consumption, and that using turboboost on a given architecture can save time and energy for different applications, while disabling turboboost consumes more time but less energy on another hardware architecture for the same applications. Moreover, this study exhibits experiments to deal with turboboost in depth, unlike other studies in the literature that start by deactivating the turboboost because of its impacts on performance and power consumption (5,6). All the data collected from the experiments of these study and presented hereafter are publicly available: https://gitlab.inria.fr/orgerie/greenavx-data.…”