Scalable behavior modeling for 3D field-programmable ESD protection structures

Wang, L.; Wang, X.; Shi, Zaifeng; Zhang, C.; Dong, Zongyu; Lu, Fei; Zhao, Hongliang; Wang, A.

doi:10.1109/cicc.2013.6658492

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…This is because ESD protection involves very complex multi-coupling effects, i.e., the electro-thermal-transient-materials-process-device-circuit-layout coupling effect [39,53]. ESD device behavior modeling has been successfully used for ESD protection design simulation, where accurate ESD device models can be developed from ESD test data, but only for given ESD devices [54,55]. The development of physics-based compact ESD device models has been hindered by many technical complexities.…”

Section: Soic Esd Modeling and Simulation Challengesmentioning

confidence: 99%

Challenges: ESD Protection for Heterogeneously Integrated SoICs in Advanced Packaging

Pan,

Li,

Hao

et al. 2024

Electronics

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Electrostatic discharge (ESD) failure is a major reliability problem for all forms of microelectronics products. ESD protection is required for all integrated circuits (ICs). As dimension scaling-down approaches its physical limit, heterogeneous integration (HI) emerges as a main pathway towards the age beyond Moore’s Law to facilitate advanced microsystem chips with extreme performance and rich functionalities. Advanced packaging is a key requirement for HI-enabled integrated systems-on-chiplets (SoIC) that require robust ESD protection solutions. This article outlines key emerging technical challenges associated with smart future SoIC microsystem superchips in the context of advanced packaging technologies.

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Section: Soic Esd Modeling and Simulation Challengesmentioning

confidence: 99%

Challenges: ESD Protection for Heterogeneously Integrated SoICs in Advanced Packaging

Pan,

Li,

Hao

et al. 2024

Electronics

View full text Add to dashboard Cite

show abstract

“…Whole-chip ESD protection circuit simulation is a challenging IC design problem due to lack of accurate ESD device models and suitable of full-chip ESD circuit simulation tools [1][2][3][4]. Consequently, the trial-and-error approaches still dominate in ESD protection design practice.…”

Section: Introduction To Hv Esd Protection Designmentioning

confidence: 99%