Scalability of network-on-chip communication architecture for 3-D meshes

Weldezion, Awet Yemane; Grange, Matt; Pamunuwa, Dinesh; Lu, Zhonghai; Jantsch, Axel; Weerasekera, Roshan; Tenhunen, Hannu

doi:10.1109/nocs.2009.5071459

Cited by 45 publications

(16 citation statements)

References 17 publications

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“…Each router has 7 input/output ports, a natural extension from a 5-port 2D router by adding two ports to make connections to the upper and lower layers [26] [31]. There are some other types of 3D routers such as the hybrid router [5] [31] [32] and MIRA [33], however, since router efficiency is out of the concept of this paper, we have chosen simple 7-port router in our simulation. The arbitration scheme of the switch allocator in the typical router structure is round-robin.…”

Section: Resultsmentioning

confidence: 99%

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model

Ebrahimi

Daneshtalab

Liljeberg

et al. 2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

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Three-Dimensional (3D) integration is a solution to the interconnect bottleneck in Two-Dimensional (2D) MultiProcessor System on Chip (MPSoC). 3D IC design improves performance and decreases power consumption by replacing long horizontal interconnects with shorter vertical ones. As the multicast communication is utilized commonly in various parallel applications, the performance can be significantly improved by supporting of multicast operations at the hardware level. In this paper, we propose a set of partitioning approaches each with a different level of efficiency. In addition, we present an advantageous method named Recursive Partitioning (RP) in which the network is recursively partitioned until all partitions contain comparable number of nodes. By this approach, the multicast traffic is distributed among several subsets and the network latency is considerably decreased. We also present Minimal Adaptive Routing (MAR) algorithm for the unicast and multicast traffic in 3D-mesh Networks-on-Chip (NoCs). The idea behind the MAR algorithm is utilizing the Hamiltonian path to provide a set of alternative paths.

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Section: Resultsmentioning

confidence: 99%

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model

Ebrahimi

Daneshtalab

Liljeberg

et al. 2011

Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

Self Cite

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“…Additionally, a low-diameter 3D NoC is studied in [7], where device architects leverage long wires to connect remote intralayer nodes. A novel layer-multiplexed 3D network architecture with vertical multiplexing and de-multiplexing links is proposed in [8], whereas a survey that summarizes the pros and cost of using various topologies for 3D NoCs can be found in [69,70]. As a conclusion we can mention that it is not possible to find an optimal NoC topology, since its efficiency depends highly on the inherent constraints posed by the target application domain.…”

Section: Fig 213 3d Mesh Topologymentioning

confidence: 99%

NoC Modeling and Topology Exploration

Tatas

Siozios

Soudris

et al. 2013

Designing 2D and 3D Network-on-Chip Architectures

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This chapter describes two of the most important tasks for designing NoC-based systems dealing with NoC modeling, as well as the topology exploration. For this purpose, state-of-the-art architectural solutions are discussed and open research topics are highlighted. Additionally, this chapter provides a description of alternative traffic models used as input to the NoC domain for evaluating the efficiency of various architectural parameters. The last topics discussed in this chapter are topology synthesis and application mapping onto the derived NoC architecture under various constraints. IntroductionWith the advent of chip multi-processors (CMP) and multi-core systems-on-chip (SoC), the network-on-chip (NoC) paradigm has been proposed as a viable solution to the problem of connecting the continuously increasing number of processing cores that are integrated on a single die. The communication problem is expected to become far more important with the demand for higher processing power posed by the majority of application domains and the technology scaling.Even though the NoC-based communication scheme introduces architectural scalability and performance enhancement, as already discussed in Chap. 1, however, careful design is absolutely required in order to achieve these gains. In this chapter, we discuss a number of architectural issues related to widely accepted NoC topologies. Additionally, the available academic and commercial solutions for topology modeling and synthesis are presented, whereas the main features/limitations for each of them are highlighted. In order to quantify the efficiency for each architectural selection, appropriate benchmarks are also required. For this purpose, throughout the second chapter we also introduce a number of typical traffic models employed for the scope of evaluating NoC architectures. Since the design, as well as the quantification of these NoC parameters are rather complex tasks, which cannot be easily performed without the usage of dedicated software tools, a number of frameworks are also introduced.K. Tatas et al., Designing 2D and 3D Network-on-Chip Architectures,

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“…A network is said to be scalable if its performance improves with the increase in number of cores. To investigate the scalability of 2-D NoC, we have focused on the key network parameters (D and E/D) which are related to latency and throughput with size of the network as depicted in [50]. For both Mesh and MoT based 2-D NoC, the values of (E/D) max and D min are computed from the above relations with increasing number of cores and is presented in the Fig.…”

Section: Scalabilitymentioning

confidence: 99%

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

Kundu

Soumya

Chattopadhyay

2012

Microprocessors and Microsystems

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Scalability of network-on-chip communication architecture for 3-D meshes

Abstract: Design Constraints imposed by global interconnect delays as well as limitations in integration of

Cited by 45 publications

References 17 publications

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model

NoC Modeling and Topology Exploration

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

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