NoC Modeling and Topology Exploration

Abstract

This chapter describes two of the most important tasks for designing NoC-based systems dealing with NoC modeling, as well as the topology exploration. For this purpose, state-of-the-art architectural solutions are discussed and open research topics are highlighted. Additionally, this chapter provides a description of alternative traffic models used as input to the NoC domain for evaluating the efficiency of various architectural parameters. The last topics discussed in this chapter are topology synthesis and application mapping onto the derived NoC architecture under various constraints. IntroductionWith the advent of chip multi-processors (CMP) and multi-core systems-on-chip (SoC), the network-on-chip (NoC) paradigm has been proposed as a viable solution to the problem of connecting the continuously increasing number of processing cores that are integrated on a single die. The communication problem is expected to become far more important with the demand for higher processing power posed by the majority of application domains and the technology scaling.Even though the NoC-based communication scheme introduces architectural scalability and performance enhancement, as already discussed in Chap. 1, however, careful design is absolutely required in order to achieve these gains. In this chapter, we discuss a number of architectural issues related to widely accepted NoC topologies. Additionally, the available academic and commercial solutions for topology modeling and synthesis are presented, whereas the main features/limitations for each of them are highlighted. In order to quantify the efficiency for each architectural selection, appropriate benchmarks are also required. For this purpose, throughout the second chapter we also introduce a number of typical traffic models employed for the scope of evaluating NoC architectures. Since the design, as well as the quantification of these NoC parameters are rather complex tasks, which cannot be easily performed without the usage of dedicated software tools, a number of frameworks are also introduced.K. Tatas et al., Designing 2D and 3D Network-on-Chip Architectures,