Saturation of threshold-voltage shift during positive bias temperature instability in HfSiON/SiO₂n-channel MOSFET and its effect on device lifetime evaluation

Abstract

This paper investigates the saturation of threshold-voltage shift ΔV th of HfSiON/SiO 2 n-channel MOSFETs (nMOFSETs) under positive bias temperature instability (PBTI) and proposes an empirical PBTI degradation model that can predict operational lifetime t L accurately. Experimental results indicate that secondary-hole trapping occurred in the bulk dielectric due to hole injection at the anode after electron trapping in the initial bulk trap. This secondary-hole trapping causes a decrease in the time exponent n of the power law ΔV th / t n as the gate stress voltage V g,str increases. This dependency of n on V g,str results in overestimation of t L when it was estimated using the conventional method which assumes a constant value of n. An empirical model that considers the effect of V g,str on n is proposed; this model predicted operational t L = 2.6 ' 10 5 s, which agreed well with experimentally-measured t L = 3.9 ' 10 5 s.

Characterization of fast relaxation by oxide-trapped charges under BTI stress on 64 nm HfSiON/SiO2 MOSFETs

“…These experimental data show that many charge trapping/de-trapping sites exist in the gate dielectric, but that they can be rapidly recovered, so the measured amount of degradation in the early stage of BTI stress was small by fast relaxation of Q ox in SM. For t s > 1 s, all curves of BTI degradation in SM can be characterized by conventional power law: 42) | | ( )…”

“…where a and n are fitted constants. In the conventional degradation model, 42) n is constant regardless of V g,str and the V g,str dependence of a is modeled as…”