Satisfiability modulo theory based methodology for floorplanning in VLSI circuits

Abstract

This paper proposes a Satisfiability Modulo Theory based formulation for floorplanning in VLSI circuits. The proposed approach allows a number of fixed blocks to be placed within a layout region without overlapping and at the same time minimizing the area of the layout region. The proposed approach is extended to allow a number of fixed blocks with ability to rotate and flexible blocks (with variable width and height) to be placed within a layout without overlap. Our target in all cases is reduction in area occupied on a chip which is of vital importance in obtaining a good circuit design. Satisfiability Modulo Theory combines the problem of Boolean satisfiability with domains such as convex optimization. Satisfiability Modulo Theory provides a richer modeling language than is possible with pure Boolean SAT formulas. We have conducted our experiments on MCNC and GSRC benchmark circuits to calculate the total area occupied, amount of deadspace and the total CPU time consumed while placing the blocks without overlapping. The results obtained shows clearly that the amount of dead space or wasted space is reduced if rotation is applied to the blocks.

SMT-Based Placement for System-on-Chip Design

“…3: Supported Orientation. From this, it can obviously be seen, that m 2 is placed between the coordinates (0, 3) and (3,6).…”

“…Therefore, the target technology directly contains the macro blocks which can be directly utilized for. 2) Macro Placement: After the design has been mapped to the target technology, the macros have to be placed on the layout [5], [2], [6]. To this end, the placement underlies cost functions like minimizing the needed die area.…”

“…Macro placement for SoC design has already been studied widely within the industrial as well as the academic research communities. These efforts led to multiple approaches including the application of meta-heuristic algorithms like Simulated Annealing (SA) [1], approaches based on Machine Learning (ML) [5], as well as Genetic Algorithms (GA) [2], or approaches based on reasoning engines [6], [9].…”

A modified relay-race algorithm for floorplanning in PCB and IC design

“…The number of components in a circuit and the interconnections between these components increase rapidly as technology improves over time [1]. Floorplanning optimizes the relative locations of the components in the layout to reduce the layout area and wire length of the interconnections, which affect the subsequent routing quality and overall physical design process significantly [2]. The representation method affects the floorplanning process, because it determines the scope of the search space and the complexity of transformation between the floorplanning representation and its corresponding floorplan.…”

DOTFloor–A Diffusion Oriented Time-Improved Floorplanner for Macrocells

“…The technique presented in [14] still consumes considerable time when included for the complete floorplan optimization process. Authors in [15] have presented a floorplan strategy built around Satisfiability Modulo Theory to handle hard as well as flexible functional blocks. In this work, optimization has been done for the chip area alone.…”