SAT-Based Image Computation with Application in Reachability Analysis

Abstract

Abstract. Image computation nds wide application in VLSI CAD, such as state reachability analysis in formal veri cation and synthesis, combinational veri cation, combinational and sequential test. Existing BDD-based symbolic algorithms for image computation are limited by memory resources in practice, while SAT-based algorithms that can obtain the image by e n umerating satisfying assignments to a CNF representation of the Boolean relation are potentially limited by time resources. We propose new algorithms that combine BDDs and SAT i n order to exploit their complementary bene ts, and to o er a mechanism for trading o space vs. time. In particular, 1 our integrated algorithm uses BDDs to represent the input and image sets, and a CNF formula to represent the Boolean relation, 2 a fundamental enhancement called BDD Bounding is used whereby the SAT solver uses the BDDs for the input set and the dynamically changing image set to prune the search space of all solutions, 3 BDDs are used to compute all solutions below i n termediate points in the SAT decision tree, 4 a ne-grained variable quanti cation schedule is used for each BDD subproblem, based on the CNF representation of the Boolean relation. These enhancements coupled with more engineering heuristics lead to an overall algorithm that can potentially handle larger problems. This is supported by our preliminary results on exact reachability analysis of ISCAS benchmark circuits.

Interpolation and SAT-Based Model Checking

“…By contrast, the present approach is based entirely on SAT, does not use quantifier elimination, and is not limited in the number of inputs (examples with thousands of inputs have been verified). SAT algorithms have also been used to generate a disjunctive decompositions for BDD-based image computations [13]. Here, BDD's are not used.…”

Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation

“…Existing BDD-based algorithms are typically limited by memory resources, while SAT-based algorithms are limited by time resources. Despite recent attempts to use SAT-based algorithms for full verification (pure SAT in [23,8,21,16] and SAT with BDDs in [19,17,18]), it is still widely acknowledged that the strength of SAT-based algorithms lies primarily in falsification, while BDD-based model checking continues to be the de facto standard for verifying properties (see surveys in [28] and [4]). The goal of this work is verification of large systems.…”

Checking consistency of C and Verilog using predicate abstraction and induction

“…This technique is commonly used in other areas, for example in [17,11] and was suggested earlier for solving quantified formulae in [21,22]. In [15], our implementation of this algorithm was applied to predicate abstraction for hardware and software systems.…”

“…McMillan [17] uses conflict graph analysis in order to enlarge the cube. Gupta et al [11] use BDDs for the enlargement. However, these techniques are beyond the scope of this article.…”