SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults

Dobai, Roland; Baláž, Marcel

doi:10.1109/dsd.2011.28

Cited by 4 publications

(5 citation statements)

References 17 publications

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“…The tests are shorter even in the cases when compared to methods with lower TDF coverages. The proposed SKEWGEN has better TDF coverages in comparison to SfW method [5] but also shorter tests for each circuit except s832, and in comparison to SKEWSAT [8] it has better TDF coverages in every case and still shorter tests for each circuit except c1355, c1908 and s832.…”

Section: Resultsmentioning

confidence: 91%

“…Many of these orders were evaluated and the one with the best TDF coverage was selected. The results achieved for this order by the method published in [8] are shown in column "reord.". The proposed SKEWGEN was evaluated with the same WBR and scan cell order for objective comparison, therefore the same TDF coverages are expected.…”

Section: Resultsmentioning

confidence: 95%

“…column of Table II shows that at the same time the test is shorter in average by 25.75% (in comparison to column "reord." which contains the results for SKEWSAT with the same TDF coverage and assuming the best fault order among the evaluated ones resulting in the shortest test, since the test length for SKEWSAT is influenced by the order of targeting the faults [8]). The generated test was longer for circuit c1355 only probably because of the presence of hardly and just individually detectable faults.…”

Section: Resultsmentioning

confidence: 98%

“…The content of the WBR is applied to the core in every clock cycle. The details about the test application were published in [8].…”

Section: Related Workmentioning

confidence: 99%

“…SAT-based test data compression was proposed in [7] and used by the skewed-load method based on satisfiability (SKEWSAT) [8] for TDFs of SOCs. SKEWSAT overcomes the limitation of the SfW method by not using a pre-generated set of vectors.…”

Section: Related Workmentioning

confidence: 99%

See 4 more Smart Citations

Genetic method for compressed skewed-load delay test generation

Dobai

Baláž

2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Complex system-on-chips (SOCs) require low-overhead testability methods to keep the test cost at an acceptable level. Skewed-load tests seem to be the appropriate way to test delay faults in these SOCs because the test application requires only one storage element per scan cell. Compressed skewedload test generator based on genetic algorithm is proposed for wrapper-based logic cores of SOCs. Deterministic populationinitialization is used to ensure the highest achievable transition delay fault coverage for the given wrapper and scan cell order. The developed genetic algorithm performs test data compression by generating test vectors containing already overlapped test vector pairs. The experimental results show high fault coverages, decreased test lengths and better scalability in comparison to recent methods.

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Section: Resultsmentioning

confidence: 91%

Section: Resultsmentioning

confidence: 95%

Section: Resultsmentioning

confidence: 98%

“…The content of the WBR is applied to the core in every clock cycle. The details about the test application were published in [8].…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 3 more Smart Citations

Genetic method for compressed skewed-load delay test generation

Dobai

Baláž

2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Techniques for SAT-based constrained test pattern generation

Balcarek

Fišer

Schmidt

2013

Microprocessors and Microsystems

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Abstract-Testing of digital circuits seems to be a completely mastered part of the design flow, but constrained test patterns generation is still a highly evolving branch of digital circuit testing. Our previous research on constrained test pattern generation proved that we can benefit from an implicit representation of test patterns set in CNF (Conjunctive Normal Form). Some techniques of speeding up the constrained SATbased test patterns generation are described and closely analyzed in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a constrained test patterns compression based on overlapping of test patterns. Experiments are performed on a subset of ISCAS'85 and '89 benchmark circuits. Results of the experiments are discussed and recommendations for a further development of similar SAT-based tools for constrained test patterns generation are given.

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