2012
DOI: 10.1049/iet-cta.2010.0440
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Sampling and controlling faster than the computational delay

Abstract: For a sampled-data control system, we propose to choose the time between samples to be shorter than the computational delay involved in computing the control signal, an approach we call intradelay sampling. It is shown that, utilising a parallel computing architecture, this is indeed feasible and that intra-delay sampling schemes yield better performance than their slower sampling counterparts.

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Cited by 8 publications
(3 citation statements)
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“…On the other hand there is a fundamental constraint for MPC design problems: in order to implement the controller in realtime, the optimization algorithm execution time has to be smaller than the sampling time of the system. There are certain exceptions to this rule [19], which are not considered in this work.…”
Section: Formulating the Design Problem As An Optimization Problemmentioning
confidence: 96%
“…On the other hand there is a fundamental constraint for MPC design problems: in order to implement the controller in realtime, the optimization algorithm execution time has to be smaller than the sampling time of the system. There are certain exceptions to this rule [19], which are not considered in this work.…”
Section: Formulating the Design Problem As An Optimization Problemmentioning
confidence: 96%
“…is the exponential function [51], [52]. The communication architecture for sensing the DER states is described in the next section.…”
Section: B Discretisation Of the Der State-space Modelmentioning
confidence: 99%
“…Intra-delay sampling can be implemented by physically replicating the solver and/or by using data pipelining, so that computation of a new solution is started before termination of previous one. Disturbance rejection capabilities of a controller can be improved as a result of the increased sampling rate [35].…”
Section: A Processorsmentioning
confidence: 99%