Abstract:Abstract-Many modern control, automation, signal processing and machine learning applications rely on solving a sequence of optimization problems, which are updated with measurements of a real system that evolves in time. The solutions of each of these optimization problems are then used to make decisions, which may be followed by changing some parameters of the physical system, thereby resulting in a feedback loop between the computing and the physical system. Real-time optimization is not the same as 'fast' … Show more
“…These tools have excellent performance in generating HDL codes for digital design beside the handwritten HDL code in the manner of time spent [47,48]. However, handwritten HDL coding always stands out in terms of area constraint, power consumption, operating speed, and getting good control performance [5,47,49,50]. Also usage of the system generator tools causes problems on implementation with floating point format because of the area constraint.…”
This study proposes an FPGA‐based hardware in the loop (HIL) emulator for speed‐sensorless of induction motor (IM) constant switching frequency controller‐based direct torque control (CSFC‐DTC) with a novel bi input‐reduced order extended Kalman filter (BI‐ROEKF). The full precision single floating point numbers in the IEEE 754 standard are used during the implementation of the HIL emulator which contains closed‐loop speed‐sensorless drive system of IM on the Xilinx Virtex XC5VLX‐110T ML506 FPGA board. In this HIL emulator of speed‐sensorless IM drive system, stator stationary axis components of stator flux, rotor mechanical angular speed, load torque, stator and rotor resistances are estimated with the novel BI‐ROEKF which is proposed for the first time in the literature. The proposed BI‐ROEKF is created by applying two different non‐linear and linear system input functions obtained from two different IM models to the single reduced order extended Kalman filter (ROEKF) algorithm. Thus, the order and the computational burden of the EKF are reduced. The HIL emulator of the speed‐sensorless drive system of IM is implemented on FPGA using the advantage of hand‐written VHDL on getting an optimal logical design to reduce the sampling time which directly effects the estimation performance of the model‐based estimator like the novel BI‐ROEKF and hence the control performance of drive system. The estimation performance of the novel BI‐ROEKF is tested with speed‐sensorless CSFC‐DTC IM drive system under different challenging scenarios in HIL emulator. Thus, the control and the implementation performances of digitalised emulator are tested. Finally, the estimation and control performance results and the execution time of the each part of the proposed HIL emulator of the speed‐sensorless BI‐ROEKF‐based CSFC‐DTC of the IM are presented.
“…These tools have excellent performance in generating HDL codes for digital design beside the handwritten HDL code in the manner of time spent [47,48]. However, handwritten HDL coding always stands out in terms of area constraint, power consumption, operating speed, and getting good control performance [5,47,49,50]. Also usage of the system generator tools causes problems on implementation with floating point format because of the area constraint.…”
This study proposes an FPGA‐based hardware in the loop (HIL) emulator for speed‐sensorless of induction motor (IM) constant switching frequency controller‐based direct torque control (CSFC‐DTC) with a novel bi input‐reduced order extended Kalman filter (BI‐ROEKF). The full precision single floating point numbers in the IEEE 754 standard are used during the implementation of the HIL emulator which contains closed‐loop speed‐sensorless drive system of IM on the Xilinx Virtex XC5VLX‐110T ML506 FPGA board. In this HIL emulator of speed‐sensorless IM drive system, stator stationary axis components of stator flux, rotor mechanical angular speed, load torque, stator and rotor resistances are estimated with the novel BI‐ROEKF which is proposed for the first time in the literature. The proposed BI‐ROEKF is created by applying two different non‐linear and linear system input functions obtained from two different IM models to the single reduced order extended Kalman filter (ROEKF) algorithm. Thus, the order and the computational burden of the EKF are reduced. The HIL emulator of the speed‐sensorless drive system of IM is implemented on FPGA using the advantage of hand‐written VHDL on getting an optimal logical design to reduce the sampling time which directly effects the estimation performance of the model‐based estimator like the novel BI‐ROEKF and hence the control performance of drive system. The estimation performance of the novel BI‐ROEKF is tested with speed‐sensorless CSFC‐DTC IM drive system under different challenging scenarios in HIL emulator. Thus, the control and the implementation performances of digitalised emulator are tested. Finally, the estimation and control performance results and the execution time of the each part of the proposed HIL emulator of the speed‐sensorless BI‐ROEKF‐based CSFC‐DTC of the IM are presented.
“…New hardware architectures have been studied for the implementation of MPC [10], including programmable logic controllers (PLCs) [11], low-cost microcontrollers [12,13], field programmable gate arrays (FPGAs) [14,15] [16], and application specific integrated circuits (ASICs) [17]. The choice of hardware architecture is often a trade-off between cost, energy consumption and required performance.…”
Model predictive control is an optimization-based strategy for high-performance control that is attracting increasing interest. While model predictive control (MPC) requires the online solution of an optimization problem, its ability to handle multivariable systems and constraints makes it a very powerful control strategy specially for MPC of embedded systems, which have an ever increasing amount of sensing and computation capabilities. We argue that the implementation of MPC on field programmable gate arrays (FPGAs) using automatic tools is nowadays possible, achieving cost-effective successful applications on fast or resource-constrained systems. The main burden for the implementation of MPC on FPGAs is the challenging design of the necessary algorithms. We outline an approach to achieve a software-supported optimized implementation of MPC on FPGAs using high level synthesis tools and automatic code generation. The proposed strategy exploits the arithmetic operations necessaries to solve optimization problems to tailor an FPGA design, which allows a trade-off between energy, memory requirements, cost, and achievable speed. We show the capabilities and the simplicity of use of the proposed methodology on two different examples and illustrate its advantages over a microcontroller implementation.
“…The key issue therefore is how to deal with this time window since, if not done with caution, the optimization problem embedded in the controller may be out of date in the face of the evolution of the real system if the controller is delayed, or perform unnecessary calculations if the controller is advanced. The suitability of a controller should not be evaluated just in a single optimization from the optimality sense, but should be evaluated according to the controller-system behavior over time [10].…”
Abstract-Due to the growth of computational capabilities and the proliferation of field-programmable gate arrays (FPGA), the utilization of model predictive control (MPC) for embedded applications in the industry has become a possibility and a fact. This paper presents and discusses the possibilities of the use of online MPC, embedded in an educational device from National Instruments, using two different optimization algorithms and code generators, which have come out in recent years by the academia: CVXGEN, which implements a primal-dual interiorpoint algorithm, and qpOASES, which relies on the online activeset strategy algorithm. Both algorithms have been tested both in simulation and in real-time experimentation to control a fourtank pilot plant.
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