RV-CAP: Enabling Dynamic Partial Reconfiguration for FPGA-Based RISC-V System-on-Chip

Charaf, Najdet; Kamaleldin, Ahmed; Thümmler, Martin; Göhringer, Diana

doi:10.1109/ipdpsw52791.2021.00033

Cited by 7 publications

(2 citation statements)

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“…V based compute tile) is implemented based on a single RISC-V core approach [37] inside the main processing tile to control and manage the reconfiguration process through the DPR technique for Xilinx FPGA. The proposed manyarchitecture consists of a static partition region and several reconfigurable partition (RP) regions to be reconfigured according to the selected many-core configuration.…”

Section: Internal Run-time Reconfiguration Managementmentioning

confidence: 99%

“…The DPR process is conducted internally through internal access configuration port (ICAP) primitive to allow AGILER architecture to self-manage the configuration process without any external controlling peripherals (e.g. a PC through a JTAG) [37]. A block diagram for the proposed reconfiguration manager is shown in Figure 6.…”

Section: Internal Run-time Reconfiguration Managementmentioning

confidence: 99%

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AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors

Kamaleldin¹,

Göhringer²

2022

IEEE Access

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Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of opensource RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Intertile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for 8x32-bit tiles and 316 MOPS for 8x64-bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex Ultrascale+ FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.INDEX TERMS Many-core architecture, parallel computing, RISC-V, network-on-chip (NoC), field programmable gate array (FPGA), reconfigurable computing.

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Section: Internal Run-time Reconfiguration Managementmentioning

confidence: 99%

Section: Internal Run-time Reconfiguration Managementmentioning

confidence: 99%