Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors

Kempf, Fabian; Hoefer, Julian; Kres, Fabian; Hotfilter, Tim; Harbaum, Tanja; Becker, Juergen

doi:10.1109/socc56010.2022.9908110

Cited by 5 publications

(1 citation statement)

References 12 publications

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“…Por ejemplo, en [34], por un lado, mediante software, se activan o desactivan diferentes mecanismos de tolerancia a fallos implementados por software, y por otro lado, se genera un conjunto de tareas para soportar estos diferentes mecanismos de tolerancia a fallos. En [35] se protege la cache, cambiando en tiempo de ejecución, entre un sistema sin protección en este elemento a un sistema con protección. Otra opción se presenta en [36], donde también se cambia en tiempo de ejecución de un sistema con dos núcleos que ejecutan tareas de forma independiente, a un sistema que junta varios núcleos para formar un núcleo lógico que permite ejecutar la misma tarea de forma replicada.…”

Section: Trabajos Previos De Tolerancia a Fallos Adaptativaunclassified

A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words

Gracia-Morán,

Saiz-Adalid,

Baraza-Calvo

et al. 2024

IEEE Latin Am. Trans.

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Actual memory systems provide large storage capacity thanks to the integration scale level achieved in CMOS technology. This increment in storage capacity comes with an augment on their fault rate. In this way, the probability of experiencing Single or Multiple Cell Upsets has risen. Error Correction Codes (ECC) are a fault-tolerant mechanism broadly employed to protect memory systems. Usually, an ECC-based fault tolerance mechanism is designed with fixed correction and detection capabilities. However, in some contexts, current memory systems can suffer a variable fault rate during their operation. Thus, it seems very interesting that this fault-tolerant mechanism would be able to adapt to these variable fault conditions. This work proposes an Adaptive Fault-Tolerant mechanism based on ECC. This mechanism can adapt to different fault conditions, being able to correct and/or detect single and multiple bits in error. The Adaptive Fault-Tolerant mechanism proposed uses a unique encoder and various decoders. Therefore, there is no need to re-encode the data to change the error coverage since the unique encoder and the equal redundancy are the same regardless of the fault tolerance required. In addition, we have studied the area, delay, and power consumption overheads produced by the inclusion of the redundant bits, the encoder, and the decoders of the ECC in a computer system.

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Section: Trabajos Previos De Tolerancia a Fallos Adaptativaunclassified