A Proposal of an ECC-based Adaptive Fault-Tolerant Mechanism for 16-bit data words
Joaquín Gracia-Morán,
Luis-J. Saiz-Adalid,
J.-Carlos Baraza-Calvo
et al.
Abstract:Actual memory systems provide large storage capacity thanks to the integration scale level achieved in CMOS technology. This increment in storage capacity comes with an augment on their fault rate. In this way, the probability of experiencing Single or Multiple Cell Upsets has risen. Error Correction Codes (ECC) are a fault-tolerant mechanism broadly employed to protect memory systems. Usually, an ECC-based fault tolerance mechanism is designed with fixed correction and detection capabilities. However, in some… Show more
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