Run-time adaptive energy-aware motion and disparity estimation in multiview video coding

Zatt, Bruno; Shafique, Muhammad; Sampaio, Felipe; Agostini, Luciano; Bampi, Sérgio; Henkel, Jörg

doi:10.1145/2024724.2024950

Cited by 46 publications

(19 citation statements)

References 15 publications

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“…Anyway, as could be noticed in Figure 7, not all of the SW must be resent every time a new MB is coded. Since MBs are coded in raster-scan order and search window of neighbouring MB overlaps, just a 16-byte-wide column update can be sent after the first complete window, as described in [28,29]. Figure 7 shows the SW for the MB N (left side) and the SW for the next MB (right side).…”

Section: H264 Encoder Implementationmentioning

confidence: 99%

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

2012

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The optimization process of a H.264/AVC encoder on three different architectures is presented. The architectures are multiand singlecore and SIMD instruction sets have different vector registers size. The need of code optimization is fundamental when addressing HD resolutions with real-time constraints. The encoder is subdivided in functional modules in order to better understand where the optimization is a key factor and to evaluate in details the performance improvement. Common issues in both partitioning a video encoder into parallel architectures and SIMD optimization are described, and author solutions are presented for all the architectures. Besides showing efficient video encoder implementations, one of the main purposes of this paper is to discuss how the characteristics of different architectures and different set of SIMD instructions can impact on the target application performance. Results about the achieved speedup are provided in order to compare the different implementations and evaluate the more suitable solutions for present and next generation video-coding algorithms.

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Section: H264 Encoder Implementationmentioning

confidence: 99%

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

2012

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“…This is especially critical during motion estimation (ME) process, which is responsible for 90% of the total memory communication in the video encoders [1].…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, the compression gains introduced by ME are penalized by its complexity and by the significant amount of external memory bandwidth required for this process. As far as memory communication significantly impacts both energy consumption and processing speed [1], the coder project must consider that a major bottleneck lies in the communication between external memory and processing units. Therefore, there is a strong need for techniques to reduce external memory communication, especially during the ME process.…”

Section: Introductionmentioning

confidence: 99%

A new differential and lossless Reference Frame Variable-Length Coder: An approach for high definition video coders

Silveira

Povala

Amaral

et al. 2014

2014 IEEE International Conference on Image Processing (ICIP)

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This paper presents a novel solution for external memory bandwidth reduction in video coding systems. The approach is based on reference frame compression, using a differential coding and a hardware-aware adaptation of the traditional Huffman algorithm, besides, it is a lossless solution fully compliant to state-of-art video coding standards, as H.264/AVC and HEVC. This solution is called DRFVLC (Differential Reference Frame Variable-Length Coder) and it uses differential coding to concentrate the samples values distribution. With the samples concentrated, an efficient static Huffman coding is applied to represent them in fewer bits. The DRFVLC reaches an average compression rate higher than 60% for the evaluated HD 1080p video sequences. This compression rate also indicates the external memory bandwidth reduction achieved with our technique. This solution can be easily implemented in hardware demanding one differentiator and a simple variable-length coder.

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“…independent encoding of each view) by employing multiple block-sized Motion and Disparity Estimation (ME, DE) that exploit temporal and interview correlations at the cost of significantly high complexity and energy consumption [3]. Typically, ME/DE accounts for more than 90% of the total MVC energy consumption, out of which the major energy consuming part is the (on-chip and off-chip) memory [7]. Therefore, memory is the key focus for energy reduction in ME and DE in order to implement MVC on battery-powered devices.…”

Section: Introduction and Related Workmentioning

confidence: 99%

“…The high memory energy consumption is primarily due to the frequent access of reference pixel data used in SAD (Sum of Absolute Differences) computations during the block matching process [7]. ME and DE search the best match of a Macroblock (MB, 16x16 pixel block) in different search directions (i.e.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Adaptive power management of on-chip video memory for multiview video coding

Shafique,

Zatt,

Walter

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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An adaptive power management of on-chip video memory for Multiview Video Coding is presented. It leverages texture, motion and disparity properties of objects and their correlations in the 3D-neighborhood. It groups different Macroblocks of a frame and predicts the highly-probable motion/disparity search direction in order to power-gate idle memory regions. Exploited are the statistical properties of Macroblock groups to predict idle sectors. Our approach achieves on average 32% and 61% energy reduction (averaged over various video sequences) compared to state-of-the-art DSW [7] and Level C [12], respectively. The Motion/Disparity Estimation architecture with video memory and power management scheme is implemented using an ASIC flow (IBM-65nm Low-Power technology) and it processes 4-view HD1080p@33fps.

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Run-time adaptive energy-aware motion and disparity estimation in multiview video coding

Cited by 46 publications

References 15 publications

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

An Efficient Multi‐Core SIMD Implementation for H.264/AVC Encoder

A new differential and lossless Reference Frame Variable-Length Coder: An approach for high definition video coders

Adaptive power management of on-chip video memory for multiview video coding

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