RTS noise reduction of 1Y-nm floating gate NAND flash memory using process optimization

Kim, Sungho; Lee, Myeongwon; Choi, Gil-Bok; Lee, Jaekwan; Lee, Yunbong; Cho, Myoungkwan; Ahn, Kun-Ok; Kim, Jinwoong

doi:10.1109/irps.2015.7112811

Cited by 2 publications

(4 citation statements)

References 5 publications

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“…However, we considered that RTN also affects regions programmed above V step from the PV level because the variation of V th in the read operation occurred even after the program was completed. In particular, reflecting the read variation by the RTN in the previous studies [18,[29][30][31][32][33][34]39], and despite the different optimal measurement conditions of RTN [31], we verified that the measured W RD s of the chip and WF in Figure 3a,c,d are larger than the W RD of RTN in Figure 3a,b. Hence, we confirmed that non−RTN factors influenced the read operation in Figure 3c,d.…”

Section: Read Variation Effect On Expansion Of Threshold Voltage Dist...supporting

confidence: 82%

“…Random telegraph noise (RTN) can be observed in the discrete fluctuations between upper and lower boundaries in V th and channel current at tens of nanometer nodes [29][30][31][32], similar to the structures in Figure 3b,d [33,34]. However, the read variation measured from the entire page is generated by undesirable effects, such as RTN, carrier transport through random grain boundaries in the polycrystalline material [35,36], common source line noise [37], and noise from the peripheral circuitry to support chip measurements [25].…”

Section: Read Variation Effect On Expansion Of Threshold Voltage Dist...mentioning

confidence: 99%

“…The Gaussian distribution of the injection probability has been previously defined as the Poisson statistics and V th distribution by RTN in a floating gate device [18]. We proceeded with the analysis of 3D structures based on CTN, the latest process technology, by extending the analysis performed in previous studies based on the floating gate device [12,18,22,30]. Despite the similar V step and lower ISPP slope (average ~0.8 compared to the floating gate with 1), the measured V th distribution is wider than the one described by the Poisson statistics and RTN [18].…”

Section: In−depth Analysis Of Over−programmingmentioning

confidence: 99%

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Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps

et al. 2023

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The incremental step pulse programming slope (ISPP) with random variation was investigated by measuring numerous three−dimensional (3D) NAND flash memory cells with a vertical nanowire channel. We stored multiple bits in a cell with the ISPP scheme and read each cell pulse by pulse. The excessive tunneling from the channel to the storage layer determines the program efficiency overshoot. Then, a broadening of the threshold voltage distribution was observed due to the abnormal program cells. To analyze the randomly varying abnormal program behavior itself, we distinguished between the read variation and over−programming in measurements. Using a 3D Monte−Carlo simulation, which is a probabilistic approach to solve randomness, we clarified the physical origins of over−programming that strongly influence the abnormal program cells in program step voltage, and randomly distributed the trap site in the nitride of a nanoscale 3D NAND string. These causes have concurrent effects, but we divided and analyzed them quantitatively. Our results reveal the origins of the variation and the overshoot in the ISPP, widening the threshold voltage distribution with traps randomly located at the nanoscale. The findings can enhance understanding of random over−programming and help mitigate the most problematic programming obstacles for multiple−bit techniques.

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Section: Read Variation Effect On Expansion Of Threshold Voltage Dist...supporting

confidence: 82%

Section: Read Variation Effect On Expansion Of Threshold Voltage Dist...mentioning

confidence: 99%

Section: In−depth Analysis Of Over−programmingmentioning

confidence: 99%

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Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps

et al. 2023

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“…Different values were found in NOR arrays, owing once more to differences in cell design and cycling conditions. Such dependences prompted several works and studies on the optimization of the cell process/architecture in order to reduce the extent of the RTN [124,[126][127][128][129][130][131][132][133][134]. In the NAND array, moreover, the RTN amplitude was shown to depend on the cell position and state along the string [135,136] (because of the different transconductances, depending on the source and drain series resistances) and on the state of cells on adjacent BLs [137] (because of the modification in the electron density profile induced by electrostatic interference).…”

Section: Main Experimental Datamentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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RTS noise reduction of 1Y-nm floating gate NAND flash memory using process optimization

Cited by 2 publications

References 5 publications

Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps

Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

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