2017 IEEE International High Level Design Validation and Test Workshop (HLDVT) 2017
DOI: 10.1109/hldvt.2017.8167464
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RTL level trace signal selection and coverage estimation during post-silicon validation

Binod Kumar
1
,
Kanad Basu
2
,
Masahiro Fujita
3
et al.
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Cited by 6 publications
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