RTL c-based methodology for designing and verifying a multi-threaded processor

Semeria, L.; Seawright, Andrew; Mehra, Renu; Ng, David C.; Ekanayake, Ashen; Pangrle, Barry

doi:10.1145/513918.513951

Cited by 24 publications

(5 citation statements)

References 13 publications

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“…This is in contrast to the work presented in [24], which assumes a one-on-one mapping of registers and variables.…”

Section: Formal Equivalence Criterionmentioning

confidence: 89%

Checking Consistency of C and Verilog using Predicate Abstraction and Induction

Clarke¹,

Kroening²

2004

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It is common practice to write C models of circuits due to the greater simulation efficiency. Once the C program satisfies the requirements, the circuit is designed in a hardware description language (HDL) such as Verilog. It is therefore highly desirable to automatically perform a correspondence check between the C model and a circuit given in HDL. We present an algorithm that checks consistency between an ANSI-C program and a circuit given in Verilog using Predicate Abstraction. The algorithm exploits the fact that the C program and the circuit share many basic predicates. In contrast to existing tools that perform predicate abstraction, our approach is SAT-based and allows all ANSI-C and Verilog operators in the predicates. We report experimental results on an out-of-order RISC processor. We compare the performance of the new technique to Bounded Model Checking (BMC).

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“…This is in contrast to the work presented in [24], which assumes a one-on-one mapping of registers and variables.…”

Section: Formal Equivalence Criterionmentioning

confidence: 89%

Checking Consistency of C and Verilog using Predicate Abstraction and Induction

Clarke¹,

Kroening²

2004

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“…Model checking of high level programs have existed for some time [15], [16]. There also exist off the shelf and research-level hardware model checkers at the netlist level [17], [18] and at CDFG level [19] with standard logic assertions.…”

Section: Related Workmentioning

confidence: 99%

A Verifiable High Level Data Path Synthesis Framework

Malazgirt

Culha

Şen

et al. 2012

2012 15th Euromicro Conference on Digital System Design

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Abstract-This work presents a synthesis framework that generates a formally verifiable RTL from a high level language. We develop an estimation model for area, delay and power metrics of arithmetic components for Xilinx Spartan 3 FPGA family. Our estimation model works 300 times faster than Xilinx's toolchain with an average error of 6.57% for delay and 3.76% for area estimations. Our framework extracts CDFGs from ANSI-C, LRH(+) [1] and VHDL. CDFGs are verified using the symbolic model checker NuSMV [2] with temporal logic properties. This method guarantees detection of hardware redundancy and wordlength mismatch related bugs by static code checking.

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“…For example, Séméria et al [20] reported verifying C against Verilog as part of a C-based design flow. However, their C model was already in RTL C, so the verification aspect was straightforward.…”

Section: Related Workmentioning

confidence: 99%

Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification

Feng

2006

Proceedings of the 43rd Annual Conference on Design Automation - DAC '06

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Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intended for synthesis. Thus, equivalence verification between the high-level software functional model and the RTL is needed. The typical approach is to convert the high-level software into RTL or gate-level hardware, via software path enumeration, symbolic execution, or highlevel synthesis techniques, and then use hardware combinational equivalence checking. The principle contribution of this paper is to introduce cutpoints -as in gate-level combinational equivalence verification -early during the analysis of the software model, thereby avoiding exponential path enumeration and the potential logical complexity blow-up of merging execution paths that can occur in the usual approach. The method is conservative, but in our experiments, we did not encounter spurious counterexamples, and the method showed large improvements in runtime and memory usage on a family of IA-32 subset instruction length decoders, an industry-suggested challenge problem.

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RTL c-based methodology for designing and verifying a multi-threaded processor

Cited by 24 publications

References 13 publications

Checking Consistency of C and Verilog using Predicate Abstraction and Induction

Checking Consistency of C and Verilog using Predicate Abstraction and Induction

A Verifiable High Level Data Path Synthesis Framework

Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification

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