RTL and refutation by positive cycles

Wang, Farn; Mok, Aloysius K.

doi:10.1007/3-540-58555-9_121

Cited by 11 publications

(11 citation statements)

References 15 publications

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“…One such logic for describing the specification and the safety assertion is Real-Time Logic (RTL). However, the satisfiability problem for RTL, as well as for other first-order logics, is undecidable [21]. In an effort to find subclasses of RTL having decidable properties, the path real-time logic (path RTL) [14,16,21] and extended path real-time logic (extended path RTL) [3] were identified and described.…”

Section: Introductionmentioning

confidence: 99%

“…However, the satisfiability problem for RTL, as well as for other first-order logics, is undecidable [21]. In an effort to find subclasses of RTL having decidable properties, the path real-time logic (path RTL) [14,16,21] and extended path real-time logic (extended path RTL) [3] were identified and described. A typical timing constraint expressed in path RTL is a disjunction of inequalities like ∀i @(e 1 , i)− @(e 2 , i) ≤ k, that has the meaning: the difference between the time of the i−th occurrence of event e 1 and the time of the i−th occurrence of event e 2 is at most k, where the time occurrence, i and k are positive integers.…”

Section: Introductionmentioning

confidence: 99%

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Verifying Linear Real-Time Logic Specifications

Andrei

Cheng

2007

28th IEEE International Real-Time Systems Symposium (RTSS 2007)

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Formal specification and verification are critical to the development of safe real-time and embedded systems, which have become increasingly complex. Real-Time Logic (RTL) has been used to describe the specification and safety assertion of real-time systems. However, the satisfiability problem for RTL, as well as other first-order logics, is undecidable. There exist already non-trivial fragments of RTL, like path RTL and extended path RTL, for which the verification can be done efficiently. The key idea used by these RTL fragments was the so-called constraint graph. The constraint graph can express dependencies between two events, but cannot describe dependencies between three or more events.This paper presents a larger class than existing fragments of RTL for which the verification problem can also be solved efficiently. Our new class is called Linear Real-Time Logic (LRTL) and includes the existing decidable RTL fragments like path RTL and extended path RTL. The LRTL class is able to express any linear timing constraint with an arbitrary number of events variables (e.g., between three or more events). The main ingredient of the LRTL class is the use of matrices instead of the constraint graph, as a more powerful data structure capable of performing the conversion from RTL to a propositional formula. The unsatisfiability of the propositional formula will ensure the safety and feasibility of the given real-time system. Experimental results show that the execution times for LRTL are better than the systems expressed in extended path RTL, and comparable with those expressed in path RTL.28th IEEE International Real-Time Systems Symposium 1052-8725/07 $25.00

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Verifying Linear Real-Time Logic Specifications

Andrei

Cheng

2007

28th IEEE International Real-Time Systems Symposium (RTSS 2007)

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“…A particular subclass of RTL formulas is the so-called path RTL, [2,3] and it has two restrictions: each arithmetic inequality may involve only two terms and an integer constant, where a term is either a variable or a function; and no arithmetic expressions with a function may take an instance of itself as an argument.…”

Section: The Real-time Logic Backgroundmentioning

confidence: 99%

“…A behavioral specification often suffices for verifying the timing properties of the system. Given the behavioral specification of a system (denoted by SP ) and a safety assertion (denoted by SA) to be analysed, the goal is to relate a given safety assertion with the system specification [1,2,3]. If SA is a theorem derivable from SP , then the system is safe.…”

Section: Introductionmentioning

confidence: 99%

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Systematic Debugging of Real-Time Systems based on Incremental Satisfiability Counting

Andrei

Chin

Cheng

et al.

11th IEEE Real Time and Embedded Technology and Applications Symposium

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Real-time logic (RTL) [1,2,3] is useful for the verification of a safety assertion with respect to the specification of a real-time system. Since the satisfiability problem for RTL is undecidable, the systematic debugging of a real-time system appears impossible. This paper provides a first step towards this challenge. With RTL, each propositional formula corresponds to a verification condition. The number of truth assignments of a propositional formula helps to determine the timing constraints which should be added or modified to the system's specification. We have implemented a tool (called SDRTL,[4]) that is able to perform systematic debugging. The confidence of our approach is high as we have evaluated SDRTL on several existing industrial-based applications.

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Automatic Verification of Pointer Data-Structure Systems for All Numbers of Processes

Wang

1999

FM’99 — Formal Methods

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Real-world concurrent software may be implemented with any number of processes which are linked together to form complex and dynamic network configurations. We formally model such concurrent software as processes running algorithms on data-structures with pointers. We show that the verification problem of such algorithms is undecidable. A new automatic approximation method is then proposed to safely verify such algorithms. The central idea is to construct a finite collective image set (CIS) which collapses reachable state representations for all implementations of all numbers of processes. Our collapsing scheme filters out unimportant information of system behaviors and results in CIS's with manageable space requirements. Analysis shows our method can automatically generate a CIS of size 1619 to verify that a version of Mellor-Crummy & Scott's algorithm preserves mutual exclusion for all numbers of processes.

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RTL and refutation by positive cycles

Cited by 11 publications

References 15 publications

Verifying Linear Real-Time Logic Specifications

Verifying Linear Real-Time Logic Specifications

Systematic Debugging of Real-Time Systems based on Incremental Satisfiability Counting

Automatic Verification of Pointer Data-Structure Systems for All Numbers of Processes

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