RRAM-based TCAMs for pattern search

Liu, Zheng; Shin, Sangho; Lloyd, Scott; Gokhale, Maya; Kim, Kyungmin; Kang, Sung-Mo

doi:10.1109/iscas.2016.7527507

Cited by 38 publications

(18 citation statements)

References 14 publications

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“…c) Training scheme of HD computing using RRAM associate memory. [88] Second, an RRAM array, together with the winner-takes-all (WTA) circuit, can directly deliver the hamming distance calculation. [77][78][79] www.advancedsciencenews.com www.advintellsyst.com computing encodes the input data into query vectors and compares them with a set of hypervectors trained from various classes.…”

Section: Rram-based Designs In Trainingmentioning

confidence: 99%

“…The PE has the duality function of memory and computation. Instead of using multiple sensing amplifiers with different thresholds, [68,88] the IFC-like ISNA circuit performs data conversion by continuous charging and discharging of a capacitor. In the computing mode, the RRAM array performs matrix multiplication, and the in situ nonlinear activation (ISNA) circuit converts the output currents to spikes.…”

Section: Spike-based Designmentioning

confidence: 99%

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Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Yan

Qiao

et al. 2019

Advanced Intelligent Systems

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In‐memory computing is a computing scheme that integrates data storage and arithmetic computation functions. Resistive random access memory (RRAM) arrays with innovative peripheral circuitry provide the capability of performing vector‐matrix multiplication beyond the basic Boolean logic. With such a memory–computation duality, RRAM‐based in‐memory computing enables an efficient hardware solution for matrix‐multiplication‐dependent neural networks and related applications. Herein, the recent development of RRAM nanoscale devices and the parallel progress on circuit and microarchitecture layers are discussed. Well suited for analog synapse and neuron implementation, RRAM device properties and characteristics are emphasized herein. 3D‐stackable RRAM and on‐chip training are introduced in large‐scale integration. The circuit design and system organization of RRAM‐based in‐memory computing are essential to breaking the von Neumann bottleneck. These outcomes illuminate the way for the large‐scale implementation of ultra‐low‐power and dense neural network accelerators.

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Section: Rram-based Designs In Trainingmentioning

confidence: 99%

Section: Spike-based Designmentioning

confidence: 99%

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Yan

Qiao

et al. 2019

Advanced Intelligent Systems

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“…4c was optimised for switching time given the relatively small voltage changes it must sense to determine a match. Table 1 shows a comparison between the TCAM developed using the proposed circuits and two competitive CMOS alternatives [3,4], as well as two non-volatile memory-based approaches [5,6]. We implemented a 256 × 144 TCAM structure (meaning the system can determine if there are any matches of an input string of 144 bits with a bank of 256 words).…”

Section: String Matching Circuitmentioning

confidence: 99%

“…This type of system can be extremely useful for intrusion detection applications where packets must be scanned to determine if they contain a malicious instruction. This system can also be used as a ternary content-addressable memory (TCAM) [3][4][5][6][7], where a particular crossbar column output indicates the location (if any) of data matching an input string. Owing to the high-density nature of nanoscale memristor crossbars, this system can provide significant area reduction when compared with even the most compact TCAM designs [5,7] while remaining competitive in terms of timing and energy.…”

mentioning

confidence: 99%

Self‐biasing memristor crossbar used for string matching and ternary content‐addressable memory implementation

et al. 2017

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A memristor crossbar-based technique for highly parallel string matching is presented. An input string can be simultaneously compared against a bank of stored words, each having a different length, due to the self-biasing nature of the crossbar circuit. This string matching system essentially acts as a ternary content-addressable memory (TCAM). Owing to the high-density nature of nanoscale memristor crossbars, this system can provide a significant area reduction when compared alternative TCAM designs while remaining competitive in terms of timing and energy.

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“…M EMRISTOR technology shows great potential for developing future computing systems beyond the von Neumann architecture [10]. This is expected to accelerate the operation of various systems including artificial neural networks (ANNs) [11], search engines [12], [13] and digital signal processors [14], [15]. Memristor is a type of ReRAM technology which consists of a thin oxide film where its resistance state can be modulated electrically.…”

Section: Introductionmentioning

confidence: 99%

FPGA-Based Memristor Emulator Circuit for Binary Convolutional Neural Networks

et al. 2020

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Binary convolutional neural networks (BCNN) have been proposed in the literature for resource-constrained IoTs nodes and mobile computing devices. Such computing platforms have strict constraints on the power budget, system performance, processing and memory capabilities. Nonetheless, the platforms are still required to efficiently perform classification and matching tasks needed in various applications. The memristor device has shown promising results when utilized for in-memory computing architectures, due to its ability to perform storage and computation using the same physical element. This is in addition to their nonlinear dynamic characteristics that can be used for various applications. Emulating the memristor operation through FPGAs implementation provides flexibility for rapid prototyping and exploration of the design space. In this paper, a FPGA-based memristor emulator circuit is implemented using a multi-bit XNOR gate as the main block for binary convolution which is followed by a memristorbased pooling layer. The BCNN layer is realized by bitwise XNOR-cell followed by wide NOR gate. The implementation has been successfully synthesized and verified using Xilinx Nexys4 FPGA with less than 1% utilization and 144.9 MHz frequency of operation. In order to test the functionality of the proposed cores, a digital implementation for the circuit was realized and verified experimentally. The experimental results show similar performance when compared to software simulation.

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RRAM-based TCAMs for pattern search

Cited by 38 publications

References 14 publications

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Self‐biasing memristor crossbar used for string matching and ternary content‐addressable memory implementation

FPGA-Based Memristor Emulator Circuit for Binary Convolutional Neural Networks

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