Roughness analysis of Si/SiGe heterostructures

Feenstra, R. M.; Lutz, M. A.; Stern, Frank; Ismail, K.; Mooney, P. M.; LeGoues, F. K.; Stanis, C.; Chu, J. O.; Meyerson, B.S.

doi:10.1116/1.587865

Cited by 60 publications

(26 citation statements)

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“…Our best fits are obtained with ∆ = 1.2-1.5 A and Λ = 40-60Å suggesting good quality interfaces. These IFR parameters are also within the range of values reported in the literature [9,11,12,18] A was also assumed by Leuliet et al in their study of GaAs/AlGaAs QCLs [13], to obtain the best agreement between theoretical and experimental total scattering rates. In all our calculations we also assume the carrier temperature T h at detection time to be related to the lattice temperature T latt according to T h = T latt +δT , where δT is a constant (i.e., T latt -independent) quantity representing the residual effects of the carrier heating produced by the laser pulse.…”

Section: Resultssupporting

confidence: 63%

Interwell relaxation times inp−Si∕SiGeasymmetric quantum well structures: Role of interface roughness

et al. 2007

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Article:Califano, M., Vinh, N.Q., Phillips, P.J. et al. (10 more We report the direct determination of non-radiative lifetimes in Si/SiGe asymmetric quantum well structures designed to access spatially indirect (diagonal) interwell transitions between heavy-hole ground states, at photon energies below the optical phonon energy. We show both experimentally and theoretically, using a six-band k·p model and a time-domain rate equation scheme, that, for the interface quality currently achievable experimentally (with an average step height ≥ 1Å), interface roughness will dominate all other scattering processes up to about 200 K. By comparing our results obtained for two different structures we deduce that in this regime both barrier and well widths play an important role in the determination of the carrier lifetime. Comparison with recently published experimental and theoretical data obtained for mid-infrared GaAs/AlGaAs multiple quantum well systems leads us to the conclusion that the dominant role of interface roughness scattering at low temperature is a general feature of a wide range of semiconductor heterostructures not limited to IV-IV materials.PACS numbers:

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Section: Resultssupporting

confidence: 63%

Interwell relaxation times inp−Si∕SiGeasymmetric quantum well structures: Role of interface roughness

et al. 2007

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“…At the same time, the values of reported from AFM measurements vary from 10-30 nm [92]. Random 2D surfaces are generated from the corresponding power spectra using a standard 2D Fourier synthesis approach [93]. The "analog" random surface is then quantised in steps to take into account the discrete nature of the interface roughness steps associated with the atomic layers in the crystalline silicon substrate [83].…”

Section: Oxide Thickness Fluctuationsmentioning

confidence: 99%

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Asenov

Brown

Davies

et al. 2003

IEEE Trans. Electron Devices

501

251

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Abstract-Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed.

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“…The phases of the elements are selected randomly, ensuring that each surface is unique. Several conditions 16 must be satisfied to ensure that the corresponding 2-D surface in real space, obtained by inverse Fourier transformation, represents a real function, H x y . Figure 7 illustrates how this random surface, H , can be used to assign the dielectric constants to the different materials in the gate oxide.…”

Section: Simulation Methodologymentioning

confidence: 99%

“…Recent studies 37 38 have shown that scattering within the channel continues to affect the I ON current in nano-scale MOSFETs, where the fully ballistic regime is never reached. The simulations were carried out for substrate acceptor concentrations 2 × 10 16 Figure 14; the solid blue curve with the square symbol is obtained excluding the ionised-impurity scattering.…”

Section: Calibration For Siomentioning

confidence: 99%

Impact of High-<I>κ</I> Gate Stacks on Transport and Variability in Nano-CMOS Devices

Watling¹,

Brown²,

Ferrari³

et al. 2008

Jnl of Comp & Theo Nano

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Scaling of Si MOSFETs beyond the 90 nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilising strained Si (SSi) channels. Additionally, high-dielectrics are expected to replace SiO 2 around or after the 45 nm node to reduce the associated gate leakage current problem, facilitating further scaling. However, in spite of significant recent technological achievements, in particular, in reducing charge trapping and crystallization of the dielectric, mobility degradation in the devices with the high-gate stacks caused, in part, by the strong soft optical phonon scattering leaves room for further performance improvement. In this work we study the impact of soft optical phonon scattering on the mobility and device performance for conventional and strained Si n-MOSFETs with high-dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 35 nm.

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Roughness analysis of Si/SiGe heterostructures

Cited by 60 publications

References 0 publications

Interwell relaxation times inp−Si∕SiGeasymmetric quantum well structures: Role of interface roughness

Interwell relaxation times inp−Si∕SiGeasymmetric quantum well structures: Role of interface roughness

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Impact of High-<I>κ</I> Gate Stacks on Transport and Variability in Nano-CMOS Devices

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