ROSE::FTTransform - A source-to-source translation framework for exascale fault-tolerance research

Lidman, Jacob; Quinlan, Daniel J.; Liao, Chunhua; McKee, Sally A.

doi:10.1109/dsnw.2012.6264672

Cited by 27 publications

(17 citation statements)

References 24 publications

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“…Last, some important source to source annotated tools/frameworks are found in the literature that help the user to apply code optimizations such as Rose [31], Orio [18] and POET [45].…”

Section: Related Workmentioning

confidence: 99%

A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

Kelefouras

Djemame

2019

J Supercomput

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The advent of data proliferation and electronic devices gets low execution time and energy consumption software in the spotlight. The key to optimizing software is the correct choice, order as well as parameters of optimizations-transformations, that has remained an open problem in compilation research for decades for various reasons. First, most of the transformations are interdependent and thus addressing them separately is not effective. Second, it is very hard to couple the transformation parameters to the processor architecture (e.g., cache size) and algorithm characteristics (e.g. data reuse); therefore compiler designers and researchers either do not take them into account at all or do it partly. Third, the exploration space, i.e., the set of all optimization configurations that have to be explored, is huge and thus searching is impractical. In this paper, the above problems are addressed for data dominant affine loop kernels, delivering significant contributions. A novel methodology is presented reducing the exploration space of six code optimizations by many orders of magnitude. The objective can be Execution Time (ET), Energy consumption (E) or the number of L1, L2 and main memory accesses. The exploration space is reduced in two phases. Firstly, by applying a novel register blocking algorithm and a novel loop tiling algorithm and secondly, by computing the maximum and minimum ET/E values for each optimization set. The proposed methodology has been evaluated for both embedded and general purpose CPUs and for seven well known algorithms, achieving high memory access, speedup and energy consumption gain values (from 1.17 up to 40) over gcc compiler, hand written optimized code and Polly. The exploration space from which the near-optimum parameters are selected, is reduced from 17 up to 30 orders of magnitude. Keywords code optimizations • data cache • register blocking • loop tiling • high performance • energy consumption • data reuse Address(es) of author(s) should be given E(total)

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“…Last, some important source to source annotated tools/frameworks are found in the literature that help the user to apply code optimizations such as Rose [31], Orio [18] and POET [45].…”

Section: Related Workmentioning

confidence: 99%

A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

Kelefouras

Djemame

2019

J Supercomput

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“…The tile and cache partition sizes as well as data array layouts which are different to those the proposed equations provide are discarded (they are inefficient), reducing the search space. We have implemented an automated C to C tool just for the studied algorithms, but a general tool can be implemented by using Rose [Lidman et al 2012] for loop tiling and [Henretty et al 2009] for data layout transformation.…”

Section: Search Spacementioning

confidence: 99%

Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache Management

Kelefouras

Κεραμίδας

Nikolaos

2018

ACM Trans. Embed. Comput. Syst.

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One of the biggest challenges in multicore platforms is shared cache management, especially for data-dominant applications. Two commonly used approaches for increasing shared cache utilization are cache partitioning and loop tiling. However, state-of-the-art compilers lack efficient cache partitioning and loop tiling methods for two reasons. First, cache partitioning and loop tiling are strongly coupled together, and thus addressing them separately is simply not effective. Second, cache partitioning and loop tiling must be tailored to the target shared cache architecture details and the memory characteristics of the corunning workloads. To the best of our knowledge, this is the first time that a methodology provides (1) a theoretical foundation in the above-mentioned cache management mechanisms and (2) a unified framework to orchestrate these two mechanisms in tandem (not separately). Our approach manages to lower the number of main memory accesses by an order of magnitude keeping at the same time the number of arithmetic/addressing instructions to a minimal level. We motivate this work by showcasing that cache partitioning, loop tiling, data array layouts, shared cache architecture details (i.e., cache size and associativity), and the memory reuse patterns of the executing tasks must be addressed together as one problem, when a (near)-optimal solution is requested. To this end, we present a search space exploration analysis where our proposal is able to offer a vast deduction in the required search space.

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“…Memory scrubbing is employed in systems with greatest need, but is expensive [20,23]. Software solutions employ redundancy and specialize fault-tolerant algorithms [7,17], application-level error checking [23], and critical MPI message validation [15]. However few general techniques have been developed, and the known general techniques introduce significant overhead for parallel applications [15,16], and consequently are rarely used.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

When is multi-version checkpointing needed?

Zheng

Chien

2013

Proceedings of the 3rd Workshop on Fault-Tolerance for HPC at Extreme Scale

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The scaling of semiconductor technology and increasing power concerns combined with system scale make fault management a growing concern in high performance computing systems. Greater variety of errors, higher error rates, longer detection intervals, and "silent" errors are all expected. Traditional checkpointing models and systems assume that error detection is nearly immediate and thus preserving a single checkpoint is sufficient for resilience.We define a richer model for future systems that captures the reality of latent errors, i.e. errors that go undetected for some time, and use it to derive optimal checkpoint intervals for systems with latent errors. With that model, we explore the importance of multi-version checkpoint systems. Our results highlight the limits of single checkpoint systems, showing that two to more than ten checkpoints may be needed to achieve acceptable error coverage. Further, to achieve reasonable system efficiency, multiple versions (two to seventeen) may be needed. We study several specific exascale machine scenarios, and the results show that two checkpoints are always beneficial, but when checkpoint overheads are reduced, as many as three checkpoints are beneficial.

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ROSE::FTTransform - A source-to-source translation framework for exascale fault-tolerance research

Cited by 27 publications

References 24 publications

A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

Combining Software Cache Partitioning and Loop Tiling for Effective Shared Cache Management

When is multi-version checkpointing needed?

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