A methodology correlating code optimizations with data memory accesses, execution time and energy consumption

Abstract

The advent of data proliferation and electronic devices gets low execution time and energy consumption software in the spotlight. The key to optimizing software is the correct choice, order as well as parameters of optimizations-transformations, that has remained an open problem in compilation research for decades for various reasons. First, most of the transformations are interdependent and thus addressing them separately is not effective. Second, it is very hard to couple the transformation parameters to the processor architecture (e.g., cache size) and algorithm characteristics (e.g. data reuse); therefore compiler designers and researchers either do not take them into account at all or do it partly. Third, the exploration space, i.e., the set of all optimization configurations that have to be explored, is huge and thus searching is impractical. In this paper, the above problems are addressed for data dominant affine loop kernels, delivering significant contributions. A novel methodology is presented reducing the exploration space of six code optimizations by many orders of magnitude. The objective can be Execution Time (ET), Energy consumption (E) or the number of L1, L2 and main memory accesses. The exploration space is reduced in two phases. Firstly, by applying a novel register blocking algorithm and a novel loop tiling algorithm and secondly, by computing the maximum and minimum ET/E values for each optimization set. The proposed methodology has been evaluated for both embedded and general purpose CPUs and for seven well known algorithms, achieving high memory access, speedup and energy consumption gain values (from 1.17 up to 40) over gcc compiler, hand written optimized code and Polly. The exploration space from which the near-optimum parameters are selected, is reduced from 17 up to 30 orders of magnitude. Keywords code optimizations • data cache • register blocking • loop tiling • high performance • energy consumption • data reuse Address(es) of author(s) should be given E(total)

Exploiting Historical Data: Pruning Autotuning Spaces and Estimating the Number of Tuning Steps

“…As a result of the parameters being designed by expert programmers, most of these search spaces are relatively small compared to some other autotuning works 12,13 -the number of tuning parameters is not needlessly excessive, and most parameters only have a few rationally-selected values to choose from. While such spaces are hard to search using methods that partially rely on local search (such as simulated annealing), because most of their dimensions are very small and discontinuous, they also contain a higher proportion of relatively fast configurations, which makes random search a viable strategy.…”

An Analytical Model for Loop Tiling Transformation

“…Due to the problem of finding the optimum tile size is very complex and includes a vast exploration space [9], in addition to general methods, a large number of algorithm-specific analytical models also exist for Matrix-Matrix Multiplication (MMM) [12] [14], Matrix-Vector Multiplication [13], tensor contractions [15], Fast Fourier Transform [10], stencil [23] and other algorithms, but the proposed approaches cannot be generalized. In particular, regarding stencil applications, there has been a long thread of research and development tackling data locality and parallelism, where many loop tiling strategies have been proposed such as overlapped tiling [26] [5], diamond tiling [2] and others.…”

A Comparison of Ryu and Pox Controllers: A Parallel Implementation

“…Researchers have suggested using parallel programming techniques, including MPI, multiprocessing, and threading, to improve the efficiency of RYU and POX. These methods can better utilize the CPU's processing capabilities [6]- [8] to improve the performance of these two controllers [9] in terms of processing speed and memory allocation. The effectiveness of parallel methods in improving the efficiency of network controllers has not been thoroughly investigated.…”