Role of ZrO2 incorporation in the suppression of negative bias illumination-induced instability in Zn–Sn–O thin film transistors

Abstract

Thin film transistors (TFTs) with In and Ga-free multicomponent Zn–Sn–Zr–O (ZTZO) channel layers were fabricated using the cosputtering approach. The incorporation of ZrO2 into the Zn–Sn–O (ZTO) films increased the contact resistance, which led to the degradation of the transport properties. In contrast, the threshold voltage shift under negative bias illumination stress (NBIS) was largely improved from −12.5 V (ZTO device) to −4.2 V (ZTZO device). This improvement was attributed to the reduction in the oxygen vacancy defects in the ZTZO film, suggesting that the photoinduced transition from VO to VO2+ was responsible for the NBIS-induced instability.

Highly stable thin film transistors using multilayer channel structure

“…15 The ionized V O 2þ charges would be accumulated at the channel/gate dielectric interface upon the application of NBS and hence exhibits a large negative V TH shift. 16 This assumption is well consistent with the increased DSS value of TFT-A and TFT-C under NBS at 60 C, as shown in Figs. 4(c) and 4(d), suggesting the creation of defect states at the channel/gate dielectric interface or in the channel layer.…”

“…16 Fig. 6(c) shows the XPS O1s spectra of a bare HfO 2 film as reference, which also exhibited similar O1s peaks approximately at the same binding energies as observed in case of ZnO film.…”

“…It has been reported that appropriate doping of the semiconductor layer could improve the gate-bias stress stability of oxide based TFTs. 16,17 However, the TFTs in these cases still show significant threshold voltage shift under gate-bias stress, indicating that substantial improvement in TFT stability still needed for the development of higher performance display devices.…”

Mechanical and electrochemical properties of nanocrystalline (Mo1−xCrx)3Si coatings: Experimental and modeling studies

“…The centre of the peak (I) located at 531.2 eV may be attributed to a combination of Cr 2 O 3 and MoO 2 , since very small chemical shifts between them are difficult to distinguish among those metal oxides by core level XPS. The peak (II) at 532.6 eV arises from the OH À ions and bound water in the surface film, which may be the adsorbed OH À impurities on the sample surface from the ambient atmosphere [44,45]. The peak (III) at 533.0 eV can be attributed to the contribution from water (H-O-H) or to the Si-O bond corresponding to silicon oxides [46].…”

Overview of electroceramic materials for oxide semiconductor thin film transistors

“…The researchers suggested that high postannealing (300°C) treatment of a-GaSnZnO TFTs produced better electrical performance and stability than those of a-IGZO TFTs due to the Ga 3+ and Sn 4+ ions. There have been many similar demonstrations to date involving Si, Al, Zr, Hf, Ga, and Sn with InZnO and ZnSnO matrices, aimed at improving electrical performance (e.g., μ fe and stability) [38][39][40][41][42][43][44][45][46][47][48][49][50][51][52].…”