Role of defect size distribution in yield modeling

Ferris-Prabhu, A.V.

doi:10.1109/t-ed.1985.22187

Cited by 85 publications

(15 citation statements)

References 6 publications

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“…Once is calculated, can be obtained by averaging over all defect diameters . Experimental data lead to the conclusion that the diameter of a defect has a density function , which decreases as between and [24], [95]. is usually the resolution limit of the lithography process [32] and is the maximum size of a defect.…”

Section: B Probability Of Failure and Critical Areamentioning

confidence: 99%

“…Let the chip consist of blocks and have an average of faults. Each block will have an average of faults, and according to the Poisson distribution, the chip yield will be (24) where is the yield of one block. When each factor in (24) is compounded separately with respect to (17), the result is (25) It is also possible that each region on the chip has a different sensitivity to defects, and thus, block has the parameters , , resulting in (26) It is important to note that the differences among the various models described in this section become more noticeable when they are used to project the yield of chips with built-in redundancy.…”

Section: B Variations On the Simple Yield Modelsmentioning

confidence: 99%

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Defect tolerance in VLSI circuits: techniques and yield analysis

1998

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Section: B Probability Of Failure and Critical Areamentioning

confidence: 99%

Section: B Variations On the Simple Yield Modelsmentioning

confidence: 99%

Defect tolerance in VLSI circuits: techniques and yield analysis

1998

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“…There is a number of models to compute random defect yield such as Seed's, the Poisson, the negative binomial, and Murphy's model (see e.g. [25]). The main difference between the various yield models is in the choice of statistics that are assumed to govern the spatial distribution of defects.…”

Section: Random Defect Yield Modeling and Critical Area Computationmentioning

confidence: 99%

Yield Analysis and Optimization

Gupta¹,

Papadopoulou²

2008

Handbook of Algorithms for Physical Design Automation

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In this chapter, we are going to discuss yield loss mechanisms, yield analysis and common physical design methods to improve yield. Yield is defined as the ratio of the number of products that can be sold to the number of products that can be manufactured. Estimated typical cost of modern 300mm or 12inch wafer 0.13 µm process fabrication plant is $2-4 billion. Typical number of processing steps for a modern integrated circuit is more than 150.Typical production cycle-time is over 6 weeks. Individual wafers cost multiple thousands of dollars. Given such huge investments, consistent high yield is necessary for faster time to profit.

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“…To this extent, the concept of defect-sensitivity is introduced, and several analytical defect size distributions are studied in conjunction with analytical yield formulae [8], [9]. As a result, a "design oriented" yield prediction methodology is developed which takes into account the layout, the process, and the environmental conditions of the manufacturing line.…”

Section: Layout Defect-sensitivity Analysismentioning

confidence: 99%

Course development in IC manufacturing

Gyvez

1994

IEEE Trans. Educ.

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Abstract-Traditional curriculum in electrical engineering separates semiconductor processing courses from courses in circuit design. As a result, manufacturing topics involving yield management, and the study of random process variations impacting circuit behavior are usually vaguely treated. The subject matter of this paper is to report a course developed at Texas A&M University to compensate for the aforementioned shortcoming. This course attempts to link technological process and circuit design domains by emphasizing aspects such as process disturbance modeling, yield modeling, and defect-induced fault modeling. In a rapidly changing environment where high-end technologies are evolving towards submicron features and towards high transistor integration, these aspects are key factors to design for manufucturubility. The paper presents the course's syllabus, a description of its main topics, and results on selected project assignments carried out during a normal academic semester.

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Role of defect size distribution in yield modeling

Cited by 85 publications

References 6 publications

Defect tolerance in VLSI circuits: techniques and yield analysis

Defect tolerance in VLSI circuits: techniques and yield analysis

Yield Analysis and Optimization

Course development in IC manufacturing

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