Rock: A High-Performance Sparc CMT Processor

Chaudhry, S.; Cypher, Robert; Ekman, Magnus; Karlsson, Martin; Landin, Anders; Yip, S.; Zeffer, Håkan; Tremblay, M.

doi:10.1109/mm.2009.34

Cited by 90 publications

(41 citation statements)

References 12 publications

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“…In Sect. 5.10, we compare the performance of the proposed dynamic instruction window resizing scheme with runahead execution [11], which is a scheme that effectively exploits both ILP and MLP, and which is used in commercial processors (the Sun Rock processor [12] and IBM Power6 [13]). Finally, in Sect.…”

Section: Discussionmentioning

confidence: 99%

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MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism

Kora

Yamaguchi

Ando

2014

IEICE Trans. Inf. & Syst.

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SUMMARYSingle-thread performance has not improved much over the past few years, despite an ever increasing transistor budget. One of the reasons for this is that there is a speed gap between the processor and main memory, known as the memory wall. A promising method to overcome this memory wall is aggressive out-of-order execution by extensively enlarging the instruction window resources to exploit memory-level parallelism (MLP). However, simply enlarging the window resources lengthens the clock cycle time. Although pipelining the resources solves this problem, it in turn prevents instruction-level parallelism (ILP) from being exploited because issuing instructions requires multiple clock cycles. This paper proposed a dynamic scheme that adaptively resizes the instruction window based on the predicted available parallelism, either ILP or MLP. Specifically, if the scheme predicts that MLP is available during execution, the instruction window is enlarged and the window resources are pipelined, thereby exploiting MLP. Conversely, if the scheme predicts that less MLP is available, that is, ILP is exploitable for improved performance, the instruction window is shrunk and the window resources are de-pipelined, thereby exploiting ILP. Our evaluation results using the SPEC2006 benchmark programs show that the proposed scheme achieves nearly the best performance possible with fixed-size resources. On average, our scheme realizes a performance improvement of 21% over that of a conventional processor, with additional cost of only 6% of the area of the conventional processor core or 3% of that of the entire processor chip. The evaluation results also show 8% better energy efficiency in terms of 1/EDP (energy-delay product).

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Section: Discussionmentioning

confidence: 99%

“…To the best of our knowledge, runahead execution is well known as one of the best schemes for exploiting both ILP and MLP in terms of performance and accommodating existing processor architectures. In fact, it has been adopted in commercial processors, including the Sun Rock processor [12] and the IBM Power6 [13].…”

Section: Comparison With Runahead Executionmentioning

confidence: 99%

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism

Kora

Yamaguchi

Ando

2014

IEICE Trans. Inf. & Syst.

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“…Rock [102,18,23] is the first commercial processor that supports hardware transactional memory, and it implements a so called best effort hardware transactional memory. In order to support transactional memory, two new instructions have been added to the SPARC instruction set -chkpt and commit.…”

Section: Best Effort Hardware Transactional Memory In Rockmentioning

confidence: 99%

“…When the hardware resources are exhausted, HyTM switches to a software transactional memory implementation. HyTM has many similarities to Hybrid TM [53], NZTM [99,98], and the best effort hardware transactional memory in Rock [102,18,23]. HyTM provides a word-based interface to the transactional memory, in contrast to Hybrid TM and NZTM that rely on an object-based interface.…”

Section: Hybrid Transactional Memory Hytmmentioning

confidence: 99%

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Transactional memory

Grahn¹

2010

Journal of Parallel and Distributed Computing

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Current and future processor generations are based on multicore architectures where the performance increase comes from an increasing number of cores on a chip. In order to utilize the performance potential of multicore architectures the programs also need to be parallel, but writing parallel programs is a non-trivial task. Transactional memory tries to ease parallel program development by providing atomic and isolated execution of code sequences, enabling software composability and protected access to shared data. In addition, transactional memory has the ability to execute atomic code sequences in parallel as long as no data conflicts occur. Transactional memory implementation proposals exist for both hardware and software, as well as hybrid solutions. This special issue on transactional memory introduces transactional memory as a concept, presents an overview of some of the most important approaches so far, and finally, includes five articles that advances the state-of-the-art in transactional memory research.

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Lock‐Free Concurrent Data Structures

Cederman

Gidenstam

et al. 2017

Programming Multi‐core and Many‐core Computing Systems

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Rock: A High-Performance Sparc CMT Processor

Cited by 90 publications

References 12 publications

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism

Transactional memory

Lock‐Free Concurrent Data Structures

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