Robustness and Balancing of Parallel-Connected Power Devices: SiC Versus CoolMOS

Abstract

Please refer to published version for the most recent bibliographic citation information. If a published version is known of, the repository item page linked to above, will contain details on accessing it.

Imbalance Current Analysis and Its Suppression Methodology for Parallel SiC MOSFETs with Aid of a Differential Mode Choke

“…According to (16)- (18), Fig. 8 demonstrates the transient imbalance current caused by unequal junction temperatures, in case of V th = 2.7 V, g m = 2.4 S, T j = 25 ℃, and I L = 30 A.…”

“…Besides, an asymmetrical circuit layout results in mismatched parasitics in power loops, common source loops, and gate loops among parallel SiC MOSFETs [15], [16]. The mismatched parasitic inductances result in asymmetrical impedances and increase the imbalance current among parallel branches [17], [18]. This article has been accepted for publication in a future issue of this journal, but has not been fully edited.…”

Robustness and reliability review of Si and SiC FET devices for more-electric-aircraft applications

“…It can be concluded that at elevated temperatures, the SiC MOSFETs are generally more avalanche rugged than the silicon SJ MOSFET. It is well known that the parasitic BJT is more easily latched at higher temperatures because of the positive temperature coefficient of the p-body resistance [7].…”

Safe-Operating-Area of Snubberless Series Connected Silicon and SiC power devices

“…8, the maximum blocking voltage of the IGBT is reached. In experimental IGBTs (where thousands of internal cells conduct current in parallel) where several IGBT cells are paralleled in the main device, failure would occur before this point due to current non-uniformity [11]. However, since a single IGBT cell is being simulated, thyristor latch-up is not properly emulated.…”