Robust transition density estimation by considering input/output transition behavior

Kim, D.; Ambler, T.

doi:10.1109/iscas.2001.922070

Cited by 4 publications

(2 citation statements)

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“…Albeit, no assurance that a critical situation is not missed can be given. Other methods [8,10] are based on heuristics that estimate the switching activity for some area of the circuit. The disadvantage is that the results obtained are estimates and may lead to false negatives or false positives.…”

Section: Estimation Of Switching Activitymentioning

confidence: 99%

“…Only given this knowledge will it be possible to identify which regions actually need intervention and require the designer's attention avoiding waste of time and resources dealing with irrelevant situations. Many methods have been proposed to estimate the switching activity in a circuit [9,12]. The method we propose is intended to find the exact worst case of switching activity and is composed of two interlocked steps that perform space and time analysis.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of the conditions for the worst case switching activity in integrated circuits

Sampaio

Monteiro

Silveira

2011

Analog Integr Circ Sig Process

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Relentless advances in IC technologies have fueled steady increases on fabricated component density and working frequencies. As feature sizes decrease to nanometer scales, an increase in switching activity per unit of area and time is observed. When extreme switching activity occurs in a small region of an integrated circuit, malfunctions may be triggered that compromise behavior. This can be either a consequence of a decrease in bias levels in the power grid caused by IR-Drop, or due to unexpected glitching on gates' outputs caused by ground bounce. For proper circuit verification, both conditions have to be accurately estimated and accounted for. Achieving this in an accurate manner for a large circuit is a very challenging problem. In this paper we propose and compare methods for the identification of the conditions leading to extreme situations of switching activity in integrated circuits. Our approach is based on both spatial and time partitioning which are used to address the accuracy and computational requirements. We propose a method for determining the exact conditions for worst case switching activity in a small circuit area during a short time interval. We then show how this method can be combined with partitioning to allow for accurate full circuit verification.

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Section: Estimation Of Switching Activitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%