Robust OPC technique using aerial image parameter

Oka, Mikio; Suzuki, Shinichiro; Kawahara, Kazuyoshi; Tsuchiya, Kensuke; Ogawa, Kensuke; Ohnuma, Hidetoshi

doi:10.1117/12.681821

Cited by 2 publications

(3 citation statements)

References 4 publications

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“…It is known that aerial image (AI) quality, represented by such qualities as image contrast or image log slope (ILS) has a strong correlation with the dose latitude of the OPC design [4]. Low contrast or ILS typically leads to small dose latitude.…”

Section: Introductionmentioning

confidence: 99%

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Production-worthy full chip image-based verification

Yu¹,

Zhang²,

Xiao³

et al. 2007

SPIE Proceedings

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At 65nm technology node and below, with the ever-smaller process window, it is no longer sufficient to apply traditional model-based verification at only the nominal condition. Full-chip, full process-window verification has started to integrate into the OPC flow at the 65nm production as a way of preventing potentially weak post-OPC designs from reaching the mask making step. Through process-window analysis can be done by way of simulating wafer images at each of the corresponding focus and exposure dose conditions throughout the process window using an accurate and predictive FEM model. Alternatively, due to the strong correlation between the post-OPC design sensitivity to dose variation and aerial image (AI) quality, the study of through-dose behavior of the post-OPC design can also be carried out by carefully analyzing the AI. These types of analysis can be performed at multiple defocus conditions to assess the robustness of the post-OPC designs with respect to focus and dose variations. In this paper, we study the AI based approach for post-OPC verification in detail.For metal layer, the primary metrics for verification are bridging, necking, and via coverage. In this paper we are mainly interested in studying bridging and necking. The minimum AI value in the open space gives an indication of its susceptibility to bridging in an over-dosed situation. Lower minimum intensity indicates less risk of bridging. Conversely, the maximum AI between the metal lines provides indication of potential necking issues in an under-dosed situation.At times, however, in a complex 2D pattern area, the location as to where the AI reaches either maximum or minimum is not obvious. This requires a full-chip, dense image-based approach to fully explore the AI profile of the entire space of the design. We have developed such an algorithm to find the AI maximums and minimums that will bear true relevance to the bridging and necking analysis. In this paper, we apply the full-chip image-based analysis to 65nm metal layers. We demonstrate the capturing of potential bridging or necking issues as identified by the AI analysis. Finally, we show the performance of the full-chip image-based verification. INTRODUCTIONAs the semiconductor industry moves to 65nm and 45nm production, systematic yield loss due to limited process window is getting more and more profound. Due to the tight design rules and CD control, the allowable focus and exposure dose variation is increasingly reduced. It is therefore required that the design and corresponding OPC be able to ensure a good process window in order to achieve good yield. The existence of a few "hot spots" in the OPC design could lead to significant reduction in the overall process window. This calls for through process window verification to be applied for production OPC design so that these "hot spots" can be identified and removed before the masks are manufactured.Traditional model-based verification tool simulates the wafer images from the post OPC design with a process model calibrated to the m...

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Section: Introductionmentioning

confidence: 99%

“…Therefore, it is desirable to have a fast way of analyzing through process window behavior of the OPC design whose runtime scales less than linearly with the number of conditions. There have been several attempts to seek faster through PW verification [4,5].…”

Section: Introductionmentioning

confidence: 99%

Production-worthy full chip image-based verification

Yu¹,

Zhang²,

Xiao³

et al. 2007

SPIE Proceedings

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“…1) In another approach, during mask data preparation (MDP) after OPC, if a hotspot is extracted, an additional modification is applied to the post-OPC layout. 2,3) To apply a more practical and effective method of hotspot fixing at both the design stage and the manufacturing stage, we have developed an automated hotspot fixer (HSF). [4][5][6][7][8][9][10] The lithography compliance check (LCC) flow utilizing the HSF is illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

Full-Chip Layout Optimization for Process Margin Enhancement Using Model-Based Hotspot Fixing System

Kobayashi¹,

Kyoh²,

Kotani³

et al. 2010

Jpn. J. Appl. Phys.

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As the design rule of integrated circuits is shrinking rapidly, it is necessary to use low-k 1 lithography technologies. With low-k 1 lithography, even if aggressive optical proximity correction is adopted, many sites become marginless spots, known as “hotspots”. For this problem, hotspot fixer (HSF) in design-for-manufacturability flow has been studied. In our previous work, we indicated the feasibility of layout modification using a simple line/space sizing rule for metal layers in 65-nm-node logic devices. However, in view of the continuous design-rule shrinkage and design complication, a more flexible modification method has become necessary to fix various types of hotspots. In this work, we have developed a brute-force model-based HSF. To further reduce the processing time, the hybrid flow of rule- and model-based HSFs is studied. The feasibility of such hybrid flow is studied by applying it to the full-chip layout modification of a logic test chip.

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Robust OPC technique using aerial image parameter

Cited by 2 publications

References 4 publications

Production-worthy full chip image-based verification

Production-worthy full chip image-based verification

Full-Chip Layout Optimization for Process Margin Enhancement Using Model-Based Hotspot Fixing System

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