Robust methods for EMC-driven routing

Abstract

Due to the application of fast device technologies and the increasing complexity of printed{ circuit boards, electromagnetic phenomena, e.g., re ections and crosstalk, gain more and more importance and may even disturb the function of a circuit. In the future, it will be indispensable to consider phenomena of electromagnetic compatibility (EMC) already during layout synthesis. In this paper, robust methods are presented that make it possible for the rst time to incorporate complex EMC{constraints and cost criteria into printed{circuit board routing. This includes both, concepts for the development and speci cation of EMC{design models and robust and e cient algorithms for EMC{driven routing which can handle these models.

EMC-driven midway routing on PCBs

“…We assume that pins are connected only to the top or bottom layer, such a s i t is common in todays SMDs. Therefore, additional vias are necessary to connect to the inner layers, and the number of vias is not comparable to the results in [13]. The most remarkable improvements are an increase of completion rate of 4 5% and a speed-up of 35 100%.…”

“…Details (e.g.,EMC-aspects) can be found in [13]. During global routing, the PCB is divided into blocks.…”

“…In the HERO-approach this is done sequentially, i.e., block b y block and net by net. For routing a single net inside a block, an extension of maze-running methods to general cost criteria is used [13]. By taking into account the net ordering and layer assignment for the determination of the net routing-order, nets blocking each other can be largely avoided.…”

“…Therefore we specify an EMC-balance for each net, determining what percentage of the overall noise is allowed for signal reections, crosstalk and so on. The assignment of portions may v ary during the synthesis process (for details see [13]). …”

“…In order to minimize the number of redesigns, EMC-eects have to be considered already during physical design. In [13] a robust hierarchical routing system (HERO) for printed-circuit boards (PCBs) has been presented that, for the rst time, incorporates complex EMC-constraints and cost criteria into all routing phases. Before, EMC-aspects have been dealt with only by applying simple EMC-cost functions [2,10,14] or simple design rules [4] to maze-running methods [7].…”