Robust Elmore delay models suitable for full chip timing verification of a 600MHz CMOS microprocessor

Nassif, Nevine; Desai, Madhav P.; Hall, Dale H.

doi:10.1145/277044.277104

Cited by 6 publications

(1 citation statement)

References 9 publications

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“…Most work uses Elmore-based delay models which uses effective resistances. This approach is known to have modeling errors and does not accurately model the effects of slew rates [12] or signals with reduced swing. Rather than cope with Elmore modeling inaccuracies, we chose to exploit the structured FPGA environment to reduce the problem space associated with FPGA interconnect design, and instead focus on more accurate HSPICE-based delay models.…”

Section: Background and Problem Formulationmentioning

confidence: 99%

Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Lee

Lemieux

Mirabbasi

2007

J Sign Process Syst Sign Image

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Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays. Given a target physical wire length, width, and spacing, the method determines the number, size, and position of buffers required to obtain the fastest signal velocity for programmable interconnect. While traditional hand-calculations used for ideal repeater placement can be used, they are not very accurate and ignore practical constraints such as the overhead effects of front-end multiplexing and driving logic, Bfinite^wire length, and a discrete number of repeaters. A metric introduced during the design is the Bpath delay profile^, or the arrival time of a signal at different points of a long wire. This method is used to design buffering strategies for interconnect based on 0.5, 2, and 3 mm wire lengths in 180 nm technology. These interconnect designs are coded into VPR along with an improved timing analyzer which accurately determines the Bpath delay profile^arrival times. Using VPR, average critical-path delay is reduced by 19% for 0.5 mm wires and by up to 46% for 3mm wires over previous designs.

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Section: Background and Problem Formulationmentioning

confidence: 99%

Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Lee

Lemieux

Mirabbasi

2007

J Sign Process Syst Sign Image

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Interconnect driver design for long wires in field-programmable gate arrays

Lee

Lemieux

Mirabbasi

2006

2006 IEEE International Conference on Field Programmable Technology

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Designers of field-programmable gate arrays (FPGAs) are always striving to improve the performance of their designs. As they migrate to newer process technologies in search of higher speeds, the challenge of interconnect delay grows larger. For an FPGA, this challenge is crucial since most FPGA implementations use many long wires. A common technique used to reduce interconnect delay is repeater insertion. Recent work has shown that FPGA interconnect delay can be improved by using unidirectional wires with a single driver at only one end of a wire. With this change, it is now possible to consider interconnect optimization techniques such as repeater insertion. In this work, a technique to construct switch driver circuit designs is developed. Using this method, it is possible to determine the driver sizing, spacing and the number of stages of the circuit design. A computer-aided design model of the new circuit designs is developed to assess the impact they have on the delay performance of FPGAs. Results indicate that, by using the presented circuit design technique, the critical path can be reduced by 19% for short wires, and up to 40% for longer wires.

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