Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs

Abstract

ABSTRACT3D integration has new manufacturing and design challenges such as timing corner mismatch between tiers and device variation due to Through Silicon Via (TSV) induced stress. Timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers. TSV induced stress is another challenge in 3D Clock Tree Synthesis (CTS). Mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. In this paper, we propose clock tree design methodology with the following objectives: (a) to minimize clock period variation by assigning optimal zlocation of clock buffers with an Integer Linear Program (ILP) formulation, (b) to prevent unwanted skew induced by the stress. In the results, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with our robust 3D CTS.

Post Silicon Management of On-Package Variation Induced 3D Clock Skew

“…Such high quality clock trees fully utilizing 3D design space can span entire dies as shown in Fig. 1 [7][8][9][10][11][12][13][14]. To safely apply highly optimized 3D clock trees distributed on multiple dies to a main production process of 3D ICs, we need to consider a new 3D process variation issue which is a special item distinguished from the conventional process variation for 2D clock trees.…”

“…3D CTS methodology with pre-bond testability is enabled by the work [11] and optimized by the work [12]. For the process variation, Xu et al [13] analyzed the process variation induced clock skew for scaled 2D and 3D ICs and Yang et al [14] proposed a process variation aware 3D CTS methodology. However, the work in [13] is only limited to the simple H-tree which is only practical to the regularly placed sink elements.…”

“…However, the work in [13] is only limited to the simple H-tree which is only practical to the regularly placed sink elements. The work in [14] did not optimize the die-todie variation in 3D stacked ICs. Moreover, the variation reduction method for clock buffers in [14] inherently can sacrifice too many TSVs.…”

“…The work in [14] did not optimize the die-todie variation in 3D stacked ICs. Moreover, the variation reduction method for clock buffers in [14] inherently can sacrifice too many TSVs.…”

20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications

“…The energy wasted by the static EC becomes more and more significant, when the process technology is scaled down [61]. 3) Thirdly, the high complexity of the conventional architecture imposed by its circuits dedicated to the different tasks increases the requirements imposed on the clock tree and on the buffers for multiple input signal loads [62]. Hence, this may impose a significant additional energy dissipation on the decoder.…”