RNS-Based Elliptic Curve Point Multiplication for Massive Parallel Architectures

Abstract

Acceleration of cryptographic applications on massive parallel computing platforms, such as Graphic Processing Units (GPUs), becomes a real challenge concerning practical implementations. In this paper, we propose a parallel algorithm for Elliptic Curve (EC) point multiplication in order to compute EC cryptography on these platforms. The proposed approach relies on the usage of the Residue Number System (RNS) to extract parallelism on high-precision integer arithmetic. Results suggest a maximum throughput of 9827 EC multiplications per second and minimum latency of 29.2 ms for a 224-bit underlying field, in a commercial Nvidia 285 GTX GPU. Performances up to an order of magnitude better in latency and 122% in throughput are achieved regarding other approaches reported in the related art. An experimental analysis of the scalability, based on OpenCL descriptions of the proposed algorithms, suggest that further advantage can be obtained from the proposed RNS approach for GPUs and EC curves supported by underlying finite fields of smaller size, regarding implementations on general purpose multi-cores.

Introduction to Residue Number System: Structure and Teaching Methodology

“…The RNS structures can be embedded in singlepurpose and application-specific processor architecture supported on extensions to the instruction-set architecture (ISA) [77]. Also, RNS is effectively used in parallel-programming of embedded systems as shown in RNS-based cryptography implemented on GPU [78].…”

RNS-Based Embedded Processor Design

“…The channel arithmetic blocks perform the modular additions, subtractions, and multiplications on each channel. These were the chosen modular operations, since they are the basic arithmetic operations required in digital signal processing [3,6,7,10,11] and in applications, such as in asymmetrical cryptography [8,9]. These arithmetic blocks are also used to perform the binary-to-RNS conversion.…”

“…Once more the final value is stored in the destination register, and in the accumulator if the flag a is set. The last three single cycle instructions (7)(8)(9), preceded by 's', have the same behaviour as the previous ones, but instead of adding the result of the operation between rs1 and rs2, subtracts that value from the accumulator. In these instructions, the flag a has the same functionality, i.e., besides the destination register, the result of the operation is also stored in the accumulator if a is set.…”

“…Digital Signal Processors (DSPs) are a key component of many digital consumer products in several application domains, such as telecommunications, digital audio, video and imaging, speech processing, cryptography, and multimedia [1][2][3][4][5][6][7][8][9]. The design of DSPs has evolved rapidly over the last decade, driven by the ever-increasing need to improve performance and balance power consumption, flexibility, and integration of more features.…”

Double Level Montgomery Cox-Rower Architecture, New Bounds

“…Due to the ability to compute any operation quickly (O(n) complexity in RNS vs O(n log 2 (3) ) in multiprecision for multiplications when using Karatsuba) without carry propagation and with natural parallelism, RNS has gained interest in the literature [11,12,1]. Recently, it has also been demonstrated to be suitable for pairing computations [3,13].…”